Output stage, amplifier control loop and use of the output stage

Abstract

An output stage includes a first transistor pair with a first conductivity type and a second transistor pair with a second conductivity type. The source connections of the first and second transistors in the first transistor pair and of the first and second transistors in the second transistor pair are respectively connected to a first and a second circuit node. The output stage further includes a first current mirror with the first conductivity type and a second current mirror with the second conductivity type. The current mirror transistors are connected to the signal output. The signal input is connected to control connections of the first transistors in the first and second transistor pairs. A second connection of the second transistor in the first transistor pair is connected to the second current mirror, and a second connection of the second transistor in the second transistor pair is connected to the first current mirror.

1 . An output stage, comprising:
 first and second differential amplifier circuits, wherein each of the first and second differential amplifier circuits comprise asymmetric transistor pairs, wherein an output current in one transistor of each transistor pair is less than a current in the other transistor of the respective transistor pair; and   first and second current mirror circuits coupled to the second and first differential amplifier circuits, respectively, wherein each of the first and second current mirror circuits comprise transistor pairs, wherein a first current mirror transistor of each current mirror circuit is coupled to the output current transistor of the respective differential amplifier circuit, and wherein a second current mirror transistor of each current mirror circuit is coupled together to form a signal output, and further wherein a current in each second current mirror transistor is greater than a current in the respective first current mirror transistor.   
     
     
         2 . The output stage of  claim 1 , wherein the transistor pair of the first differential amplifier circuit comprises transistors of a first conductivity type and the transistor pair of the second differential amplifier circuit comprises transistors of a second conductivity type, and wherein the transistor pair of the first current mirror circuit comprises transistors of the first conductivity type and the transistor pair of the second current mirror circuit comprises transistors of the second conductivity type. 
     
     
         3 . The output stage of  claim 2 , wherein each transistor pair comprises transistors of different sizes. 
     
     
         4 . The output stage of  claim 3 , wherein an amount of difference in the sizes of the transistors in the transistor pairs of the first and second differential amplifier circuits dictate an amount of quiescent current in the output stage, and an amount of difference in the sizes of the transistors in the transistor pairs of the first and second current mirror circuits dictate a maximum current limit of the output stage. 
     
     
         5 . An output stage, comprising:
 a signal input, an actuating input, and a signal output;   a first transistor pair, where a respective first connection of a first transistor and of a second transistor in the first transistor pair is connected to a first circuit node;   a first current source connected to the first circuit node;   a second transistor pair, where a respective first connection of a first transistor and of a second transistor in the second transistor pair is connected to a second circuit node;   a second current source connected to the second circuit node;   a first current mirror connected to the signal output; and   a second current mirror connected to the signal output, wherein the signal input is connected to the first transistors in the first and second transistor pairs, the actuating input is connected to the second transistors in the first and second transistor pairs, a second connection of the second transistor in the first transistor pair is connected to the second current mirror, and a second connection of the second transistor in the second transistor pair is connected to the first current mirror.   
     
     
         6 . The output stage of  claim 5 , further comprising a charge store coupled between the signal input and the signal output. 
     
     
         7 . The output stage of  claim 5 , wherein the first and second current mirrors are formed with bipolar transistors. 
     
     
         8 . The output stage of  claim 7 , wherein an emitter area of the current mirror transistor in the first and second current mirrors is larger by a factor than an emitter area of a further transistor in the first and second current mirrors, respectively. 
     
     
         9 . The output stage of  claim 5 , wherein the first transistor pair comprise p-channel field effect transistors and the second transistor pair comprise n-channel field effect transistors. 
     
     
         10 . The output stage of  claim 9 , wherein the first transistor in the first transistor pair has a channel width and a channel length whose ratio forms a geometric parameter, and wherein the geometric parameter differs from a geometric parameter formed from a channel width and a channel length of the second transistor in the first transistor pair by a first factor that is greater than 1. 
     
     
         11 . The output stage of  claim 10 , wherein the first transistor in the second transistor pair has a channel width and a channel length whose ratio forms a geometric parameter, and wherein the geometric parameter differs from a geometric parameter formed from a channel width and a channel length of the second transistor in the second transistor pair by a second factor that is greater than 1. 
     
     
         12 . The output stage of  claim 5 , wherein at least one of the first and second transistor pairs comprise bipolar transistors. 
     
     
         13 . The output stage of  claim 12 , wherein the first transistor pair comprises pnp bipolar transistors and the second transistor pair comprises npn bipolar transistors. 
     
     
         14 . The output stage of  claim 13 , wherein an emitter area of the first transistor in the first transistor pair differs by a factor greater than 1 from an emitter area of the second transistor in the first transistor pair. 
     
     
         15 . The output stage of  claim 13 , wherein an emitter area of the first transistor in the second transistor pair differs by a factor greater than 1 from an emitter area of the second transistor in the second transistor pair. 
     
     
         16 . The output stage of  claim 11 , wherein the first factor and the second factor are the same. 
     
     
         17 . The output stage  claim 5 , wherein:
 the first current mirror comprises another transistor whose control connection is connected to a control connection of the current mirror transistor in the first current mirror;   the second current mirror comprises another transistor whose control connection is connected to a control connection of the current mirror transistor in the second current mirror;   the another transistors and the current mirror transistors have a respective associated geometric parameter which is derived from geometric dimensions of the respective transistors and current mirror transistors; and   the geometric parameter of the current mirror transistor in the first and second current mirrors is greater by a factor than the geometric parameter of the another transistors.   
     
     
         18 . The output stage of  claim 5 , wherein the first circuit node is coupled to a supply potential, and the second circuit node is coupled to a reference potential. 
     
     
         19 . The output stage of  claim 5 , wherein a second connection of the first transistor in the first transistor pair is connected to a supply potential, and a second connection of the first transistor in the second transistor pair is connected to a reference potential.