Amplifier circuit and radio receiver

Abstract

A feedback resistor is connected between an input terminal and an output terminal of an operational amplifier. A negative resistor is connected between an inverting input terminal and a non-inverting input terminal of the operational amplifier.

1 . An amplifier circuit comprising:
 an operational amplifier;   a feedback resistor connected between an input terminal and an output terminal of the operational amplifier; and   a negative resistor connected between an inverting input terminal and a noninverting input terminal of the operational amplifier.   
     
     
         2 . The amplifier circuit according to  claim 1 , wherein the negative resistor includes:
 a pair of field effect transistors, a drain of one of which is connected to a gate of the other; and   a bias current source that supplies a bias current to sources of the field effect transistors.   
     
     
         3 . The amplifier circuit according to  claim 2 , wherein the bias current source includes:
 a first field effect transistor, a gate of which is connected to a drain thereof;   a second field effect transistor, a gate of which is connected to the gate of the first field effect transistor;   a third field effect transistor, a drain of which is connected to the drain of the first field effect transistor;   a fourth field effect transistor, a gate and a drain of which are connected to a drain of the second field effect transistor;   a fifth field effect transistor, a gate of which is connected to the drain of the second field effect transistor;   a sixth field effect transistor, a gate and a drain of which are connected to a drain of the fifth field effect transistor;   a seventh field effect transistor, a gate of which is connected to the gate of the sixth field effect transistor; and   a resistor connected to a source of the second field effect transistor.   
     
     
         4 . The amplifier circuit according to  claim 3 , wherein
 gate widths of the third field effect transistor and the fourth field effect transistor are set the same, and   gate width of the second field effect transistor is set to be larger than gate width of the first field effect transistor.   
     
     
         5 . The amplifier circuit according to  claim 1 , wherein the negative resistor includes:
 a pair of first field effect transistors, a drain of one of which is connected to a gate of the other;   a first bias current source that supplies a bias current to sources of the first field effect transistors;   a pair of second field effect transistors connected in series with the first field effect transistors, gates of the second field effect transistors being connected to each other; and   a second bias current source that supplies a bias current to sources of the second field effect transistors.   
     
     
         6 . The amplifier circuit according to  claim 1 , wherein the negative resistor includes:
 a pair of first field effect transistors, a drain of one of which is connected to a gate of the other;   a first bias current source that supplies a bias current to sources of the first field effect transistors;   a pair of second field effect transistors connected in series with the first field effect transistors, a drain of one of the second field effect transistors being connected to a gate of the other; and
 a second bias current source that supplies a bias current to sources of the second field effect transistors. 
   
     
     
         7 . The amplifier circuit according to  claim 1 , wherein the negative resistor includes:
 a pair of first field effect transistors, a drain of one of which is connected to a gate of the other;   a bias current source that supplies a bias current to sources of the first field effect transistors;   a pair of second field effect transistors connected in series with the first field effect transistors, a drain of one of the second field effect transistors being connected to a gate of the other;   a detection circuit that detects voltage between terminals of the negative resistor; and
 a third field effect transistor that controls, based on a detection result of the detection circuit, a bias current supplied to sources of the second field effect transistors. 
   
     
     
         8 . An amplifier circuit comprising:
 an operational amplifier;   a feedback resistor connected between an inverting input terminal and an output terminal of the operational amplifier; and   a negative resistor connected to the inverting input terminal of the operational amplifier.   
     
     
         9 . The amplifier circuit according to  claim 8 , wherein power consumption of the operational amplifier is set such that noise caused by the negative resistor is smaller than noise caused by the operational amplifier. 
     
     
         10 . The amplifier circuit according to  claim 8 , further comprising an input resistor connected to the inverting input terminal and the noninverting input terminal of the operational amplifier. 
     
     
         11 . The amplifier circuit according to  claim 10 , wherein the negative resistor cancels a resistor component that depends on the input resistor and the feedback register. 
     
     
         12 . The amplifier circuit according to  claim 8 , wherein the negative resistor includes:
 a field effect transistor;   an inverter inserted between a drain and a gate of the field effect transistor; and   a bias current source that supplies a bias current to a source of the field effect transistor.   
     
     
         13 . The amplifier circuit according to  claim 12 , wherein the bias current source includes:
 a first field effect transistor, a gate of which is connected to a drain thereof;   a second field effect transistor, a gate of which is connected to the gate of the first field effect transistor;   a third field effect transistor, a drain of which is connected to the drain of the first field effect transistor;   a fourth field effect transistor, a gate and a drain of which are connected to a drain of the second field effect transistor;   a fifth field effect transistor, a gate of which is connected to the drain of the second field effect transistor;   a sixth field effect transistor, a gate and a drain of which are connected to a drain of the fifth field effect transistor;   a seventh field effect transistor, a gate of which is connected to the gate of the sixth field effect transistor; and   a resistor connected to a source of the second field effect transistor.   
     
     
         14 . The amplifier circuit according to  claim 8 , wherein the negative resistor includes:
 a field effect transistor;   an inverter inserted between a drain and a gate of the field effect transistor;   a first bias current source that supplies a bias current to a source of the field effect transistor; and   a second bias current source that supplies a bias current to the drain of the field effect transistor.   
     
     
         15 . The amplifier circuit according to  claim 8 , wherein the negative resistor includes:
 a first field effect transistor;   a first inverter inserted between a drain and a gate of the first field effect transistor;   a first bias current source that supplies a bias current to a source of the first field effect transistor;   a second field effect transistor, a drain of which is connected to the drain of the first field effect transistor;   a second inverter inserted between the drain and a gate of the second field effect transistor; and   a second bias current source that supplies a bias current to a source of the second field effect transistor.