Semiconductor device and manufacturing methods with using non-planar type of transistors

Abstract

Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.

1 . A method of forming a static random access memory cell, comprising:
 forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor; and   widening a width of the assist-fin to form an assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.   
     
     
         2 . The method of  claim 1 , wherein the assist-fin is formed by a sidewall image transfer technique. 
     
     
         3 . The method of  claim 1 , wherein the assist-fin is widened by silicon epitaxial process, silicidation process, or combinations thereof. 
     
     
         4 . The method of  claim 1 , wherein the assist-fin is widened by silicon epitaxial process and then silicidation process. 
     
     
         5 . The method of  claim 1 , wherein portions of the fins of the non-planar pull-up transistor and non-planar pull-down transistor are widened at the same time when widening the assist-fin. 
     
     
         6 . A method of fowling a random logic circuit, comprising:
 forming an assist-fin between fins of non-planar transistors on a semiconductor substrate; and   widening a width of the assist-fin to form an assist-bar so that a portion of the fin of one non-planar transistor is electrically connected to a portion of the fin of another non-planar transistor via the assist-bar.   
     
     
         7 . A method of decreasing a cell area of a static random access memory cell comprising two non-planar pass-gate transistors, two non-planar pull-up transistors, and two non-planar pull-down transistors, the method comprising:
 electrically connecting a portion of a fin of the non-planar pull-up transistor and a portion of a fin of the non-planar pull-down transistor by an assist-bar.   
     
     
         8 . The method of  claim 6 , wherein electrically connecting the portion of the fin of the non-planar pull-up transistor and the portion of the fin of the non-planar pull-down transistor by an assist-bar comprises:
 forming an assist-fin between the fins of the non-planar pull-up transistor and the non-planar pull-down transistor; and   widening a width of the assist-fin to form the assist-bar so that the portion of the fin of non-planar pull-up transistor is electrically connected to the portion of the fin of non-planar pull-down transistor via the assist-bar.   
     
     
         9 . The method of  claim 7 , wherein the assist-fin is widened by silicon epitaxial process, silicidation process, or combinations thereof. 
     
     
         10 . The method of  claim 6 , wherein the assist-bar electrically connecting diffusion layers of the pass-gate transistor, the pull-down transistor, and the pull-up transistor. 
     
     
         11 . A method of decreasing an area of a random logic circuit comprising two or more non-planar transistors, the method comprising:
 electrically connecting a portion of a fin of one non-planar transistor and a portion of a fin of another non-planar transistor by an assist-bar.