Method for fabricating semiconductor device

Abstract

A method for fabricating a semiconductor device includes forming a plurality of patterns, forming an etch target layer to gap-fill the plurality of patterns, forming an impurity region in the etch target layer, and performing an etch-back process on the etch target layer using the impurity region as an etch stop barrier.

1 . A method for fabricating a semiconductor device comprising:
 forming a plurality of patterns;   forming an etch target layer to gap-fill the plurality of patterns;   forming an impurity region in the etch target layer; and   performing an etch-back process on the etch target layer using the impurity region as an etch stop barrier.   
     
     
         2 . The method of  claim 1 , wherein the plurality of patterns are formed to have different widths, respectively, and different depths, respectively. 
     
     
         3 . The method of  claim 1 , wherein the plurality of patterns are formed to have the same width and the same depth. 
     
     
         4 . The method of  claim 1 , wherein the forming of the impurity region includes performing an ion implantation process. 
     
     
         5 . The method of  claim 1 , wherein the forming of the impurity region includes implanting an impurity into the etch target layer. 
     
     
         6 . The method of  claim 5 , wherein the impurity includes a P-type impurity. 
     
     
         7 . The method of  claim 6 , wherein the etch target layer includes an undoped material or an N-type impurity doped material. 
     
     
         8 . The method of  claim 6 , wherein the P-type impurity includes boron. 
     
     
         9 . The method of  claim 1 , wherein the etch target layer includes a silicon layer. 
     
     
         10 . The method of  claim 1 , wherein the performing of the etch-back process includes using a plasma. 
     
     
         11 . The method of  claim 1 , wherein the forming of the plurality of patterns includes using a hard mask as an etch barrier in forming the plurality of patterns and the performing of the etch-back process includes performing an etch-back process using the hard mask. 
     
     
         12 . The method of  claim 11 , wherein, in length, the thickness of the hard mask is less than the depth that the impurity region lies from the top surface of the hard mask. 
     
     
         13 . A method for fabricating a semiconductor device comprising:
 forming a plurality of patterns;   forming an etch target layer to gap-fill the plurality of patterns;   forming a first impurity region in the etch target layer;   performing a first etch-back process on the etch target layer using the first impurity region as a first etch stop barrier;   forming a second impurity region in the remaining etch target layer; and   performing a second etch-back process on the remaining etch target layer using the second impurity region as a second etch stop barrier.   
     
     
         14 . The method of  claim 13 , wherein the plurality of patterns are formed to have different widths, respectively, and different depths, respectively. 
     
     
         15 . The method of  claim 13 , wherein the forming of the first impurity region and the forming of the second impurity region each include performing an ion implantation process. 
     
     
         16 . The method of  claim 13 , wherein the forming of the first impurity region includes implanting an impurity into the etch target layer and the forming of the second impurity region includes implanting the impurity into the remaining etch target layer. 
     
     
         17 . The method of  claim 16 , wherein the impurity includes a P-type impurity. 
     
     
         18 . The method of  claim 17 , wherein the etch target layer includes an undoped material and an N-type impurity doped material. 
     
     
         19 . A method for fabricating a semiconductor device comprising:
 forming a plurality of patterns;   forming a polysilicon layer to gap-fill the plurality of patterns;   forming a P-type impurity region in the polysilicon layer; and   performing a plasma etch-back process on the polysilicon layer using the P-type impurity region as an etch stop barrier.   
     
     
         20 . The method of  claim 19 , wherein the plurality of patterns are formed to have different widths, respectively, and different depths, respectively.