Atomic memory device

Abstract

In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command.

1 . A method of operation within an integrated-circuit memory device, the method comprising:
 retrieving a first data value from an address-specified location within a memory core of the memory device in response to a memory access command;   outputting the first data value from the memory device in response to the memory access command; and   storing a second data value in the address-specified location within the memory core in response to the memory access command.   
     
     
         2 . The method of  claim 1  wherein retrieving a first data value from an address-specified location within a memory core of the memory device comprises retrieving a first data value from a column of sense amplifiers within a sense amplifier bank of the memory device. 
     
     
         3 . The method of  claim 2  further comprising transferring data from a row of storage cells to the sense amplifier bank in a row activation operation carried out prior to receipt of the memory access command, wherein the row of storage cells forms part of a storage array within the memory core. 
     
     
         4 . The method of  claim 2  wherein storing a second data value in the address-specified location within the memory core comprises storing the second value within the column of sense amplifiers. 
     
     
         5 . The method of  claim 1  wherein outputting the firs data value from the memory device in response to the memory access command comprises outputting the first data value onto a data path external to the memory device. 
     
     
         6 . The method of  claim 1  further comprising modifying the first data value in response to the memory access command to generate the second data value. 
     
     
         7 . The method of  claim 6  wherein modifying the first data value comprises incrementing the first data value in response to the memory access command such that the second data value is an incremented version of the first data value. 
     
     
         8 . The method of  claim 6  wherein modifying the first data value comprises performing an logical operation in which the first data value constitutes a first operand and a third data value constitutes a second operand. 
     
     
         9 . The method of  claim 8  further comprising receiving the third data value from a register within the memory device. 
     
     
         10 . The method of  claim 8  further comprising receiving the third data value via an external data path. 
     
     
         11 . The method of  claim 10  wherein receiving the third data value via an external data path comprises receiving the third data value via the external data path concurrently with receiving the memory access command via an external command path. 
     
     
         12 . The method of  claim 8  wherein the logical operation comprises an arithmetic operation. 
     
     
         13 . The method of  claim 1  further comprising receiving the second data value via an external data path prior to outputting the first data value from the memory device, and wherein outputting the first data value from the memory device comprises outputting the first data value via the external data path. 
     
     
         14 . The method of  claim 1  further comprising comparing the first data value with the second data value to generate a comparison result, and wherein storing the second data value in the address-specified location within the memory core comprises conditionally storing the second data value in the address-specified location according to the comparison result. 
     
     
         15 . The method of  claim 14  wherein conditionally storing the second data value in the address-specified location according to the comparison result comprises storing the second data value in the address-specified location only if the comparison result indicates that an aspect of the second data value exceeds a corresponding aspect of the first data value. 
     
     
         16 . An integrated-circuit memory device comprising:
 a memory core; and   core access circuitry to retrieve a first data value from an address-specified location within the memory core in response to a memory access command and to store a second data value in the address-specified location within the memory core in response to the memory access command.   
     
     
         17 . The integrated-circuit memory device of  claim 16  wherein the core access circuitry comprises:
 control logic to receive the memory access command and a corresponding memory address and to enable access to the address-specified location in response to the memory access command and corresponding memory address; and 
 data input/output (I/O) circuitry to receive the first data value from the address-specified location in the memory core via the control logic and to output the first data value from the integrated-circuit memory device. 
 
     
     
         18 . The integrated circuit device of  claim 17  wherein the data I/O circuitry comprises a data receive circuit to receive the second data value via an external signaling path in response to the memory access command. 
     
     
         19 . The integrated circuit device of  claim 17  wherein the data I/O circuitry comprises a data receive circuit to receive a third data value via an external signaling path in association with the memory access command, and modify logic circuitry coupled to receive the third data value from the data receive circuit and the first data value from the memory core, the modify logic circuitry including circuitry to generate the second data value using the first and third data values. 
     
     
         20 . The integrated-circuit memory device of  claim 17  wherein the data I/O circuitry comprises modify logic circuitry coupled to receive the first data value from the memory core and having circuitry to generate the second data value by modifying the first data value. 
     
     
         21 . The integrated-circuit memory device of  claim 17  wherein the data I/O circuitry comprises a data receive circuit to receive the second data value via an external signaling path in response to the memory access command. 
     
     
         22 . The integrated-circuit memory device of  claim 21  further comprising modify logic coupled to receive the second data value from the data receive circuit and the first data value from the memory core, the modify logic circuitry including circuitry to compare the first and second data values to generate a comparison result, and to conditionally enable the second data value to be stored in the address-specified location within the memory core depending on the comparison result. 
     
     
         23 . The integrated circuit memory device of  claim 17  further comprising a register to store the second data value prior to receipt of the memory access command. 
     
     
         24 . The integrated-circuit memory device of  claim 16  wherein the memory core comprises plurality of dynamic random access memory cells. 
     
     
         25 . The integrated-circuit memory device of  claim 16  wherein the memory core comprises a plurality of flash memory cells. 
     
     
         26 . An integrated-circuit memory device comprising:
 a memory core;   means for retrieving a first data value from an address-specified location within the memory core in response to a memory access command;   means for outputting the first data value from the memory device in response to the memory access command; and   means for storing a second data value in the address-specified location within the memory core in response to the memory access command.   
     
     
         27 . A manufacture comprising one or more computer-readable storage media, the computer-readable storage media having information embodied therein that describes a physical implementation of an integrated circuit device, the information including descriptions of:
 a memory core; and   core access circuitry to retrieve a first data value from an address-specified location within the memory core in response to a memory access command and to store a second data value in the address-specified location within the memory core in response to the memory access command.