Semiconductor device including protrusion type isolation layer

Abstract

A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion.

1 .- 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a semiconductor layer including an active region;   an isolation layer surrounding the active region;   at least two gate structures crossing the active region, wherein an uppermost surface of each of the gate structure is at a level higher than an uppermost surface of the active region;   a contact plug disposed on the active region between the gate structures; and   a bit line electrically connected to the contact plug.   
     
     
         22 . The semiconductor device as claimed in  claim 21 , wherein the contact plug has a same width as the active region between the gate structures. 
     
     
         23 . The semiconductor device as claimed in  claim 21 , wherein the gate structure comprising:
 a gate insulating layer disposed on the active region;   a gate conductive layer disposed on the gate insulation layer; and   a capping layer disposed on the gate conductive layer.   
     
     
         24 . The semiconductor device as claimed in  claim 23 , wherein the gate conductive layer is buried in the semiconductor layer. 
     
     
         25 . The semiconductor device as claimed in  claim 23 , wherein the gate insulation layer disposed at a lowermost surface and side surfaces of the gate conductive layer. 
     
     
         26 . The semiconductor device as claimed in  claim 23 , wherein the capping layer extends over the uppermost surface of the active region. 
     
     
         27 . The semiconductor device as claimed in  claim 23 , wherein an uppermost surface of the gate conductive layer is at a level lower than an lowermost surface of the contact plug. 
     
     
         28 . The semiconductor device as claimed in  claim 23 , wherein an uppermost surface of the gate insulation layer is at a level lower than an lowermost surface of the contact plug. 
     
     
         29 . The semiconductor device as claimed in  claim 23 , wherein at least one side surface of the contact plug contacts the capping layer. 
     
     
         30 . The semiconductor device as claimed in  claim 23 , wherein the gate conductive layer comprises TiN, W or both. 
     
     
         31 . The semiconductor device as claimed in  claim 23 , wherein the capping layer comprises SiN. 
     
     
         32 . The semiconductor device as claimed in  claim 21 , further comprising:
 an insulating layer disposed between the semiconductor layer and the bit line.   
     
     
         33 . The semiconductor device as claimed in  claim 21 , wherein the bit line extends with a predetermined angle from the gate structure. 
     
     
         34 . The semiconductor device as claimed in  claim 33 , wherein the predetermined angle is a right angle.