Apparatus and method for reducing photo leakage current for tft lcd

Abstract

In one aspect of the invention, the method of forming a TFT array panel includes forming a patterned first conductive layer on a substrate, forming a gate insulating layer on the patterned first conductive layer and the substrate, forming a patterned semiconductor layer on the gate insulating layer, forming a patterned second conductive layer, forming a patterned passivation layer on the patterned second conductive layer and the substrate, and forming a patterned transparent conductive layer on the patterned passivation layer.

1 . A thin film transistor (TFT) array panel for a liquid crystal display device, comprising:
 (i) a substrate;   (ii) a patterned first conductive layer having a gate line, a gate electrode, and a shielding portion that is adjacent to the gate line, all formed on the substrate, the shielding portion being electrically floated;   (iii) a gate insulating layer formed on the first patterned conductive layer;   (iv) a patterned semiconductor layer formed on the gate insulating layer, having a portion that overlaps the shielding portion;   (v) a patterned second conductive layer having a source electrode and a drain electrode disposed on the patterned semiconductor layer, and a data line electrically connected to the source electrode;   (vi) a patterned passivation layer, formed on the source electrode, the drain electrode and the data line, and exposing a portion of the drain electrode; and   (vii) a transparent conductive layer having a pixel electrode formed on the patterned passivation layer and electrically connected to the drain electrode through a contact hole.   
     
     
         2 . The TFT array panel of  claim 1 , wherein the shielding portion is substantially rectangular. 
     
     
         3 . The TFT array panel of  claim 1 , wherein the gate line, the shielding portion are formed as the same layer. 
     
     
         4 . The TFT array panel of  claim 1 , wherein the data line is disposed on the patterned semiconductor layer. 
     
     
         5 . The TFT array panel of  claim 1 , wherein the pixel electrode overlaps at least a portion of the gate line, thereby forming a storage capacitor. 
     
     
         6 . The TFT array panel of  claim 1 , wherein the gate electrode and the shielding portion are separated with a gap. 
     
     
         7 . The TFT array panel of  claim 6 , wherein the width of the gap is less than 6 μm. 
     
     
         8 . The TFT array substrate panel of  claim 1 , further comprising a shielding line, disposed on the substrate and under the date line. 
     
     
         9 . The TFT array panel of  claim 1 , wherein the shielding portion is formed to have a width that is at least equal to the width of the source electrode. 
     
     
         10 . The TFT array panel of  claim 1 , wherein the patterned semiconductor layer comprises an intrinsic semiconductor layer and a doped semiconductor layer. 
     
     
         11 . The TFT array panel of  claim 1 , wherein the drain electrode is an elongated conductive bar with a first end, and an opposite, second end, and the source electrode is a “U” shaped conductive layer formed on the patterned semiconductor layer, and wherein the source electrode substantially surrounds the first end of the drain electrode to form a “U” shaped channel area. 
     
     
         12 . The TFT array panel of  claim 1 , wherein the shielding portion is not overlapped with the data line.