Logic circuit and method of logic circuit design

Abstract

A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal.

1 . A complementary logic circuit, comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a first logic block comprising:
 a p-type transistor network for implementing a predetermined logic function, said p-type transistor network comprising a plurality of p-type transistors, and having an outer diffusion connection, a first network gate connection, and an inner diffusion connection, 
 said outer diffusion connection of said p-type transistor network being connected to said first dedicated logic terminal, and said first network gate connection of said p-type transistor network being connected to said first logic input; and 
   a second logic block comprising:
 an n-type transistor network implementing logic function complementary to said predetermined logic function, said n-type transistor network comprising a plurality of n-type transistors, and having an outer diffusion connection, a first network gate connection, and an inner diffusion connection, 
 said outer diffusion connection of said n-type transistor network being connected to said second dedicated logic terminal, and said first network gate connection of said n-type transistor network being connected to said second logic input; 
   said inner diffusion connections of said p-type transistor network and of said n-type transistor network being connected to form a common diffusion logic terminal.   
     
     
         2 . A complementary logic circuit according to  claim 1 , wherein said first and second logic inputs are connected to form a first common logic input. 
     
     
         3 . A complementary logic circuit according to  claim 1 , wherein each of said logic terminals is separately configurable to serve as a logic input. 
     
     
         4 . A complementary logic circuit according to  claim 1 , wherein each of said logic terminals is separately configurable to serve as a logic output. 
     
     
         5 . A complementary logic circuit according to  claim 1 , further comprising a third logic input connected to a second network gate connection of said p-type transistor network. 
     
     
         6 . A complementary logic circuit according to  claim 1 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         7 . A complementary logic circuit according to  claim 5 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         8 . A complementary logic circuit according to  claim 7 , said third and fourth logic inputs being connected to form a second common logic input. 
     
     
         9 . A complementary logic circuit according to  claim 1 , wherein said p-type transistor network comprises one of a group of networks comprising: a network of p-type field effect transistors (FET), a network of p-type p-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type n-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type twin-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type silicon on insulator (SOI) transistors, and a network of p-type silicon on sapphire (SOS) transistors. 
     
     
         10 . A complementary logic circuit according to  claim 1 , wherein said n-type transistor network comprises one of a group of networks comprising: a network of n-type FETs, a network of n-type p-well CMOS transistors, a network of n-type n-well CMOS transistors, a network of n-type twin-well CMOS transistors, a network of n-type SOI transistors, and a network of n-type SOS transistors. 
     
     
         11 . A logic circuit, comprising interconnected logic elements, said logic elements comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a p-type transistor, having an outer diffusion connection, a gate connection, and an inner diffusion connection; and   an n-type transistor, having an outer diffusion connection, a gate connection, and an inner diffusion connection;   said first logic input being connected to said gate connection of said p-type transistor, said second logic input being connected to said gate connection of said n-type transistor, said first dedicated logic terminal being connected to said outer diffusion connection of said p-type transistor, said second dedicated logic terminal being connected to said outer diffusion connection of said n-type transistor, and said inner diffusion connection of said p-type transistor and said inner diffusion connection of said n-type transistor being connected to form a common diffusion logic terminal.   
     
     
         12 . A logic circuit according to  claim 11 , wherein for each of logic elements said first and second logic inputs are connected to form a common logic input. 
     
     
         13 . A logic circuit according to  claim 11 , wherein for each of logic elements each of said logic terminals is separately configurable to serve as a logic input. 
     
     
         14 . A logic circuit according to  claim 11 , wherein for each of logic elements each of said logic terminals is separately configurable to serve as a logic output. 
     
     
         15 . A logic circuit, comprising interconnected logic elements, said logic elements comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a first logic block comprising:
 a p-type transistor network for implementing a predetermined logic function, said p-type transistor network comprising a plurality of p-type transistors, and having an outer diffusion connection, a first network gate connection, and an inner diffusion connection, 
 said outer diffusion connection of said p-type transistor network being connected to said first dedicated logic terminal, and said first network gate connection of said p-type transistor network being connected to said first logic input; and 
   a second logic block comprising:
 a n-type transistor network implementing logic function complementary to said predetermined logic function, said n-type transistor network comprising a plurality of n-type transistors, and having an outer diffusion connection, a first network gate connection, and an inner diffusion connection, 
 said outer diffusion connection of said n-type transistor network being connected to said second dedicated logic terminal, and said first network gate connection of said n-type transistor network being connected to said second logic input; 
   said inner diffusion connections of said p-type transistor network and of said n-type transistor network being connected to form a common diffusion logic terminal.   
     
     
         16 . A logic circuit according to  claim 15 , wherein for each of said logic elements said first and second logic inputs are connected to form a first common logic input. 
     
     
         17 . A logic circuit according to  claim 15 , wherein for each of said logic elements each of said logic terminals is separately configurable to serve as a logic input. 
     
     
         18 . A logic circuit according to  claim 15 , wherein for each of said logic elements each of said logic terminals is separately configurable to serve as a logic output. 
     
     
         19 . A logic circuit according to  claim 15 , further comprising a third logic input connected to a second network gate connection of said p-type transistor network. 
     
     
         20 . A logic circuit according to  claim 15 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         21 . A complementary logic circuit according to  claim 19 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         22 . A complementary logic circuit according to  claim 21 , said third and fourth logic inputs being connected to form a second common logic input. 
     
     
         23 . A logic circuit according to  claim 15 , further comprising at least one buffer element. 
     
     
         24 . A logic circuit according to  claim 15 , further comprising at least one inverter. 
     
     
         25 . A logic element comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a p-type transistor, having an outer diffusion connection, a gate connection, and an inner diffusion connection; and   an n-type transistor, having an outer diffusion connection, a gate connection, and an inner diffusion connection;   said first logic input being connected to said gate connection of said p-type transistor, said second logic input being connected to said gate connection of said n-type transistor, said first dedicated logic terminal being connected to said outer diffusion connection of said p-type transistor, said second dedicated logic terminal being connected to said outer diffusion connection of said n-type transistor, and said inner diffusion connection of said p-type transistor and said inner diffusion connection of said n-type transistor being connected to form a common diffusion logic terminal, said first and second logic inputs being configured as independent inputs.   
     
     
         26 . A logic element according to  claim 25 , wherein each of said logic terminals is separately configurable to serve as a logic input. 
     
     
         27 . A logic element according to  claim 25 , wherein each of said logic terminals is separately configurable to serve as a logic output.