Semiconductor circuit, scanning circuit and display device using these circuits

Abstract

In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.

1 . A semiconductor circuit comprising:
 a signal input terminal for receiving an input signal;   an output terminal for outputting an output signal;   first and second clock terminals for receiving first and second clock signals, respectively;   a refresh terminal for receiving a refresh signal;   first and second power supply terminals connected to first and second power supplies, respectively;   first and second transistors connected between said first clock terminal and said first power supply terminal;   third and fourth transistors connected between said refresh terminal and said first power supply terminal; and   fifth and sixth transistors connected between said second power supply terminal and said first power supply terminal;   wherein said fourth and fifth transistors have respective control terminals connected in common to said signal input terminal;   said third transistor has a control terminal connected to said second clock terminal;   said first transistor has a control terminal connected to a first node at which said fifth and sixth transistors are connected;   said second transistor has a control terminal connected to a control terminal of said sixth transistor and to a second node at which said third and fourth transistors are connected;   a third node at which said first and second transistors are connected is connected to said output terminal; and   said refresh signal that is supplied to said refresh terminal is activated responsive to a rising edge of each of said first and second clock signals and has a period shorter than a period of each of said first and second clock signals that are input respectively to said first and second clock terminals.   
     
     
         2 . The semiconductor circuit according to  claim 1 , wherein said first to sixth transistors comprise thin-film transistors. 
     
     
         3 . The semiconductor circuit according to  claim 1 , wherein a clock signal complementary with respect to said clock signal that is supplied to the first clock terminal is supplied to said second clock terminal. 
     
     
         4 . A scan circuit having the semiconductor circuit as set forth in  claim 1 . 
     
     
         5 . A display device having the scan circuit as set forth in  claim 4 .