Semiconductor device and manufacturing method of the same

Abstract

The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate.

1 . A method for forming a semiconductor device in which an active cell which causes a load current to flow therethrough, a sense cell which detects a magnitude of the load current flowing through the active cell, and an inactive cell which separates the active cell and the sense cell from each other, are formed in a semiconductor substrate, said method comprising the steps of:
 (a) forming a first semiconductor region of a first conduction type over a first surface of the semiconductor substrate corresponding to the first conduction type;   (b) forming a trench having a depth unextended to the semiconductor substrate in the first semiconductor region;   (c) forming a third semiconductor region of a second conduction type corresponding to a conduction type opposite to the first conduction type in a lower portion of the trench;   (d) forming a first insulating film over a bottom face of the trench and a side surface thereof;   (e) forming a dummy gate electrode inside the trench via the first insulating film;   (f) eliminating part of the first insulating film formed over the side surface of the trench;   (g) forming a second insulating film over the dummy gate electrode and eliminating part of the first insulating film thereby to form a gate insulating film in the side surface of the trench exposed;   (h) forming a gate electrode over the dummy gate electrode via the second insulating film interposed therebetween and inside the trench; and   (i) introducing an impurity of the second conduction type within the first semiconductor region thereby to form a second semiconductor region,   wherein after the (i) step, a source region comprising a semiconductor region of the first conduction type is formed in a region lying within the second semiconductor region and aligned with the trench in each of an active cell forming area for forming the active cell and a sense cell forming area for forming the sense cell, and the source region is not formed in an inactive cell forming area for forming the inactive cell.   
     
     
         2 . The method according to  claim 1 , wherein the third semiconductor region formed in the (c) step is in contact with the semiconductor substrate.