Conserving power in a computer system

Abstract

A power management unit (PMU) may determine an optimal power saving state using a break-even period of a power saving state and an expected idle duration based on a first policy. The PMU may determine the optimal power saving state using a first break even period and actual idle duration based on a second policy. The break-even period may equal a minimum time a computer system should remain in a power saving state to compensate for the power consumed by the system to enter and exit that power saving state. The expected idle time duration is determined as an average of idle duration and a recent sample of idle duration. The actual idle duration is the difference of a first and second time point that represents entry and exit points to and from the power saving state. The PMU may transition the system to the optimal power saving state.

1 . A method for conserving power in a computer system, comprising:
 determining a high power saving state as an optimal power saving state if an activity level on a network is lower than a first activity value and idle periods are longer than a first set of reference values,   determining a low power saving state as the optimal power saving state the activity level on the network is higher a second activity value and the idle periods are shorter than a second set of reference values, and transitioning the computer system to the optimal power saving state.   
     
     
         2 . The method of  claim 1  further comprises determining an intermediate power saving state between the high and low power saving states based on the activity level of the network is between the first and the second activity value and the duration of the idle periods is between the first and the second set of reference values. 
     
     
         3 . The method of  claim 2 , wherein the optimal power saving state is based on one or more attributes of the high power saving state, wherein the one or more attributes include entry latency and the exit latency into the high power saving state. 
     
     
         4 . The method of  claim 3 , wherein the one or more attributes of the high power saving state includes a power consumed while the computer system is in the high power saving state. 
     
     
         5 . The method of  claim 3 , wherein the one or more attributes of the high power saving state includes a power consumed by the computer system while resuming from the high power saving state to the low power saving state. 
     
     
         6 . The method of  claim 1  further includes,
 generating a state value based on the optimal power saving state, 
 generating a control signal based on the state value, and 
 powering off one or more components of the computer system based on the control signal. 
 
     
     
         7 . The method of  claim 1  further includes,
 generating a state value based on the optimal power saving state, 
 generating a control signal based on the state value, and 
 gating clock signal provided to one or more components of the computer system based on the control signal.