Semiconductor device, electronic apparatus and semiconductor device fabricating method

Abstract

There is provided a semiconductor device which includes a primary semiconductor chip 11 , a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11 , primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21 , secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.

1 . A semiconductor device comprising:
 a semiconductor chip assembly; and   a sealing resin having a low modulus of elasticity which seals and fully encapsulates the semiconductor chip assembly,   wherein the sealing resin comprises: a primary sealing resin having a low modulus of elasticity that seals a lower surface side of the semiconductor chip assembly; and a secondary sealing resin having a low modulus of elasticity that seals all other surface sides of the semiconductor chip assembly,   wherein the semiconductor chip assembly includes a pad on an upper surface of a semiconductor chip of the semiconductor chip assembly, said pad being electrically connected to an upper surface of an external connecting terminal by a wire,   wherein a surface of the external connecting terminal that is opposite to the upper surface of the external connecting terminal connected by the wire is exposed from the secondary sealing resin, and   wherein the semiconductor chip assembly overlays a portion of the upper surface of the external connecting terminal, said portion of the upper surface of the external connecting terminal which is overlayed by the semiconductor chip assembly directly contacting the lower surface side of the semiconductor chip assembly.   
     
     
         2 . The semiconductor device as set forth in  claim 1 , wherein the semiconductor chip assembly defines an outer periphery and the sealing resin directly and fully covers the outer periphery of the semiconductor chip assembly. 
     
     
         3 . The semiconductor device as set forth in  claim 2 , wherein the semiconductor chip assembly comprises:
 a primary semiconductor chip; and   a secondary semiconductor chip stacked on the primary semiconductor chip,   wherein the outer periphery of the semiconductor chip assembly includes outer surfaces of primary semiconductor chip and the secondary semiconductor chip that are not in contact with one another.   
     
     
         4 . The semiconductor device as set forth in  claim 1 , wherein the modulus of elasticity of the primary sealing resin is greater than or equal to 1 MPa and less than or equal to 1 GPa and the modulus of elasticity of the secondary sealing resin is greater than or equal to 1 MPa and less than or equal to 1 GPa. 
     
     
         5 . The semiconductor device as set forth in  claim 1 , wherein the external connecting terminal projects into the sealing resin. 
     
     
         6 . The semiconductor device as set forth in  claim 1 , wherein the exposed surface of the external connecting terminal is flush with a surface of the secondary sealing resin. 
     
     
         7 . The semiconductor device as set forth in  claim 1 , wherein an extending portion of the upper surface of the external connecting terminal extends from the semiconductor chip assembly into the secondary sealing resin, and the wire connecting the external connecting terminal to the pad on the upper surface of the semiconductor chip is directly connected to the extending portion of the upper surface of the external connecting terminal. 
     
     
         8 . The semiconductor device as set forth in  claim 1 , wherein a height between the surface of the external connecting terminal exposed from the secondary sealing resin and the upper surface of the external connecting terminal equals a height between the lower surface side of the semiconductor chip assembly and a lower surface of the primary sealing resin. 
     
     
         9 . The semiconductor device as set forth in  claim 1 , wherein the exposed surface of the external connecting terminal is flush with a surface of the secondary sealing resin and level with a lower surface of the primary sealing resin. 
     
     
         10 . The semiconductor device as set forth in  claim 9 , wherein a height of the external connecting terminal equals a height of the primary sealing resin, said height of the external connecting terminal measured between the upper surface of the external connecting terminal and the exposed surface of the external connecting terminal, and said height of the primary sealing resin measured between the lower surface side of the semiconductor chip assembly and an exposed surface of the primary sealing resin. 
     
     
         11 . A semiconductor device comprising:
 a semiconductor chip assembly having a primary semiconductor chip and a secondary semiconductor chip stacked on the primary semiconductor chip;   a sealing resin having a low modulus of elasticity which seals and fully encapsulates the semiconductor chip assembly;   a primary external connecting terminal to which the primary semiconductor chip is connected; and   a secondary external connecting terminal to which the secondary semiconductor chip is connected,   wherein the semiconductor chip assembly further includes a pad on an upper surface side of the primary semiconductor chip that is electrically connected to an upper surface of the primary external connecting terminal by a wire, and a pad on an upper surface side of the secondary semiconductor chip that is electrically connected to an upper surface of the secondary external connecting terminal by a wire,   wherein lower surfaces of the primary and secondary external connecting terminals, which are respectively opposite to the upper surfaces of the primary and secondary external connecting terminals, are exposed from the sealing resin, and wherein the secondary semiconductor chip is stacked on the primary semiconductor chip in such a manner as not to overlap the pad on the upper surface side of the primary semiconductor chip, and   wherein the primary semiconductor chip overlays a portion of the upper surface of the primary external connecting terminal and a portion of the upper surface of the secondary external connecting terminal; said portions of the upper surfaces of the primary and secondary external connecting terminals directly contacting the lower surface side of the primary semiconductor chip.   
     
     
         12 . The semiconductor device as set forth in  claim 11 , wherein at least one of the primary and secondary external connecting terminals projects into the sealing resin. 
     
     
         13 . The semiconductor device as set forth in  claim 11 , wherein the exposed surface of at least one of the primary and secondary external connecting terminals is flush with a surface of the sealing resin. 
     
     
         14 . The semiconductor device as set forth in  claim 11 , wherein
 an extending portion of the upper surface of the primary external connecting terminal extends from the primary semiconductor chip into the sealing resin,   an extending portion of the upper surface of the secondary external connecting terminal extends from the primary semiconductor chip into the sealing resin,   the wire connecting the primary external connecting terminal to the pad on the upper surface of the primary semiconductor chip is directly connected to the extending portion of the upper surface of the primary external connecting terminal, and   the wire connecting the secondary external connecting terminal to the pad on the upper surface of the secondary semiconductor chip is directly connected to the extending portion of the upper surface of the secondary external connecting terminal.   
     
     
         15 . The semiconductor device as set forth in  claim 11 , wherein a length of the exposed lower surface of the primary external connecting terminal is less than a length of the exposed lower surface of the secondary external connecting terminal, and a distal end of the secondary external connecting terminal is disposed further away from the primary semiconductor chip than the a distal end of the primary external connecting terminal. 
     
     
         16 . The semiconductor device as set forth in  claim 11 , wherein a height of the primary external connecting terminal equals a height of the secondary external connecting terminal, said height of the primary external connecting terminal measured between the lower surface and upper surface of the primary external connecting terminal, and said height of the secondary external connecting terminal measured between the lower surface and upper surface of the secondary external connecting terminal. 
     
     
         17 . The semiconductor device as set forth in  claim 11 , wherein the exposed lower surfaces the primary and secondary external connecting terminals are level with a lower surface of the sealing resin. 
     
     
         18 . The semiconductor device as set forth in  claim 17 , wherein a height of the primary external connecting terminal equals a height of the secondary external connecting terminal, said height of the primary external connecting terminal measured between the lower surface and upper surface of the primary external connecting terminal, and said height of the secondary external connecting terminal measured between the lower surface and upper surface of the secondary external connecting terminal.