US2012133425A1PendingUtilityA1

Booster circuit and voltage supply circuit

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Assignee: MAEJIMA HIROSHIPriority: Aug 28, 2006Filed: Feb 3, 2012Published: May 31, 2012
Est. expiryAug 28, 2026(~0.1 yrs left)· nominal 20-yr term from priority
Inventors:Hiroshi Maejima
H02M 3/07
50
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Claims

Abstract

A booster circuit includes a pump circuit having a plurality of charge pump circuits that output a boosted voltage. The booster circuit also includes a clock adjusting circuit that generates a second clock signal for operating the charge pump circuits from a first clock signal to a first output terminal. The booster circuit additionally includes a pump controlling circuit that outputs the first clock signal for operating the pump circuit, a first comparator that outputs a first output signal, a second comparator that outputs a second output signal, and a third comparator that outputs a third output signal. A gradient of the boosted voltage is decreased when the first output signal is output. A frequency of the first clock signal is reduced when the second output signal is output. The third output signal is output when the boosted voltage is higher than a set value of the boosted voltage.

Claims

exact text as granted — not AI-modified
1 . A booster circuit comprising:
 a pump circuit having a plurality of charge pump circuits that output a boosted voltage;   a clock adjusting circuit that generates a second clock signal for operating said charge pump circuits from a first clock signal to a first output terminal;   a pump controlling circuit that outputs the first clock signal for operating said pump circuit;   a first comparator that outputs a first output signal;   a second comparator that outputs a second output signal; and   a third comparator that outputs a third output signal,   wherein a gradient of the boosted voltage is decreased when the first output signal is output,   a frequency of the first clock signal is reduced when the second output signal is output, and   the third output signal is output when the boosted voltage is higher than a set value of the boosted voltage.   
     
     
         2 . A booster circuit according to  claim 1 , wherein an amplitude of the first clock signal is reduced when the set value of the boosted voltage is set lower. 
     
     
         3 . A booster circuit according to  claim 1 , further comprising a limiter circuit capable of adjusting a current flowing through a first variable resistor connected to the first output terminal, a second variable resistor connected to one end of the first resistor and a third variable resistor connected to one end of the second resistor. 
     
     
         4 . A booster circuit according to  claim 1 , wherein
 the first comparator outputs the first output signal when the boosted voltage is higher than a first voltage, and   the second comparator outputs the second output signal when the boosted voltage is higher than a second voltage.   
     
     
         5 . A booster circuit according to  claim 4 , wherein
 the second voltage is higher than the first voltage, and   the set value of the boosted voltage is higher than the second voltage.   
     
     
         6 . A booster circuit according to  claim 1 , wherein the boosted voltage raises after the third output signal is output, and then comes down. 
     
     
         7 . A booster circuit according to  claim 1 , wherein the first output signal is a signal to reduce the number of active charge pump circuits. 
     
     
         8 . A booster circuit according to  claim 1 , wherein the third output signal is a signal to bring the pump circuit into an inactive state. 
     
     
         9 . A booster circuit according to  claim 1 , wherein the pump controlling circuit receives the first, second and third output signals, and controls the pump circuit. 
     
     
         10 . A booster circuit according to  claim 4 , wherein the pump controlling circuit receives the first, second and third output signals, and controls the pump circuit. 
     
     
         11 . A booster circuit according to  claim 10 , wherein the first output signal is a signal to reduce the number of active charge pump circuits. 
     
     
         12 . A booster circuit according to  claim 10 , wherein the third output signal is a signal to bring the pump circuit into an inactive state.

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