Method and apparatus for providing a packet buffer random access memory

Abstract

The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching.

1 . A packet buffer random access memory (PBRAM) device, comprising:
 (a) a single memory array;   (b) a plurality of input and output ports to be coupled to a network controller device, the single memory array for storing packet data received by the plurality of input ports being shared by the plurality of input and output ports; and   (c) a plurality of serial registers associated with the input and output ports, the serial registers simultaneously receiving packet data from the input ports and writing packet data to the memory array, the serial registers further being segmented into a plurality of segments, segments of respective serial registers being associated with corresponding portions of the memory array, segments of different serial registers simultaneously transferring packet data to different portions of the memory array.