High-performance one-transistor memory cell

Abstract

One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.

1 . A semiconductor structure, comprising:
 a semiconductor substrate with diffusion regions adapted to provide a negative differential resistance (NDR) response, the diffusion regions including a first diffusion region, a second diffusion region, a third diffusion region and a fourth diffusion region, the first and third diffusion regions of a first type, the second and fourth diffusion regions of a second type, the second diffusion region positioned between the first diffusion region and the third diffusion region, and the third diffusion region positioned between the second diffusion region and the fourth diffusion region;   a gate separated from the second diffusion region by a gate insulator;   a first conductor line connected to the first diffusion region;   a second conductor line connected to the fourth diffusion region;   a third conductor line connected to the gate; and   wherein the semiconductor structure is adapted to conduct charge between the first and second conductor lines through the first, second, third and fourth diffusion regions.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising:
 an access transistor, wherein the access transistor includes the first, second and third diffusion regions, the gate and the gate insulator; and   a diode, wherein the diode includes the third and fourth diffusion regions,   
     
     
         3 . The semiconductor structure of  claim 1 , wherein the first diffusion region is an n+ region, the second diffusion region is a p− region, the third diffusion region is a n+ region, and the fourth diffusion region is a p+ region. 
     
     
         4 . A semiconductor structure, comprising:
 a semiconductor substrate with diffusion regions adapted to provide a negative differential resistance (NDR) response, the diffusion regions including a first diffusion region, a second diffusion region, a third diffusion region, an intrinsic region, and a fourth diffusion region, the first and third diffusion regions of a first type, the second and fourth diffusion regions of a second type, the second diffusion region positioned between the first diffusion region and the third diffusion region, the third diffusion region positioned between the second diffusion region and the fourth diffusion region, and the intrinsic region positioned between the third diffusion region and the fourth diffusion region;   a gate separated from the second diffusion region by a gate insulator;   a first conductor line connected to the first diffusion region;   a second conductor line connected to the fourth diffusion region;   a third conductor line connected to the gate; and   wherein the semiconductor structure is adapted to conduct charge between the first and second conductor lines through the first, second, third and fourth diffusion regions.   
     
     
         5 . The semiconductor structure of  claim 4 , wherein:
 an access transistor includes the first, second and third diffusion regions, the gate and the gate insulator; and   a diode includes the third and fourth diffusion regions.   
     
     
         6 . The semiconductor structure of  claim 4 , wherein the first type includes an n-type dopant and the second type includes a p-type dopant. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein the first and third diffusion regions are n+ regions, the second diffusion region is a p− region, and the fourth region is a p+ region. 
     
     
         8 . The semiconductor structure of  claim 4 , wherein the NDR response includes a forward breakover point such that, when biased beyond the forward breakover point, more current can be conducted at lower voltages. 
     
     
         9 . A semiconductor structure, comprising:
 a semiconductor substrate with diffusion regions adapted to provide a negative differential resistance (NDR) response, the diffusion regions including a first n-type diffusion region, a second p-type diffusion region, a third n-type diffusion region, an intrinsic region, and a fourth p-type diffusion region, the second p-type diffusion region positioned between the first n-type diffusion region and the third n-type diffusion region, the third n-type diffusion region positioned between the second p-type diffusion region and the fourth p-type diffusion region, and the intrinsic region positioned between the third n-type diffusion region and the fourth p-type diffusion region;   a gate separated from the second p-type diffusion region by a gate insulator;   a first conductor line connected to the first n-type diffusion region;   a second conductor line connected to the fourth p-type diffusion region;   a third conductor line connected to the gate; and   wherein the semiconductor structure is adapted to conduct charge between the first and second conductor lines through the first, second, third and fourth diffusion regions.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein the first n-type diffusion region includes an n+ diffusion region, the second p-type diffusion region includes a p− diffusion region, the third n-type diffusion region includes a n+ diffusion region, and the fourth p-type diffusion region includes a p+ diffusion region. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein:
 an access transistor includes the first n-type diffusion region, the second p-type diffusion region, the third n-type diffusion region, the gate and the gate insulator; and   a diode includes the third n-type diffusion region, and the fourth p-type diffusion region.   
     
     
         12 . A semiconductor structure, comprising:
 a negative differential resistance (NDR) device connected between a first conductor and a second conductor, the NDR device adapted to provide an NDR response that includes a forward breakover point such that, when biased beyond the forward breakover point, more current can be conducted at lower voltages;   a gate positioned to assist with switching between high and low conduction states of the NDR device associated with current flow between the first and second conductors through the NDR device;   an access transistor connected between the first conductor and the NDR device, wherein the NDR device is a diode connected between the access transistor and the second conductor;   a first diffusion region, a second diffusion region, a third diffusion region, an intrinsic region, and a fourth diffusion region;   the first and third diffusion regions of a first type and the second and fourth diffusion regions of a second type;   the second diffusion region positioned between the first diffusion region and the third diffusion region, the third diffusion region positioned between the second diffusion region and the fourth diffusion region, and the intrinsic region positioned between the third diffusion region and the fourth diffusion region;   the gate separated from the second diffusion region by a gate insulator; and   the access transistor including the first, second and third diffusion regions, and the diode including the third and fourth diffusion regions.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein the first and third diffusion regions are n-type regions and the second and fourth diffusion regions are p-type regions. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein the first diffusion region is an n+ region, the second diffusion region is a p− region, the third diffusion region is a n+ region, and the fourth diffusion region is a p+ region. 
     
     
         15 . The semiconductor structure of  claim 14 , wherein the p− region is adapted to function as a transistor body region and the n+ regions are adapted to function as transistor source/drain regions. 
     
     
         16 . A semiconductor structure, comprising:
 a substrate adapted to conduct current through a channel between a first conductor and a second conductor, the channel including first, second, third and fourth diffusion regions between the first and second conductors, the first and third diffusion regions of a first conductivity type and the second and fourth diffusion regions of a second conductivity type, the channel further including an intrinsic region positioned between the third and fourth diffusion regions; and   a gate separated from the second diffusion region by a gate insulator.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein:
 the channel has a negative differential resistance (NDR) response that includes a forward breakover point such that, when biased beyond the forward breakover point, more current can be conducted at lower voltages; and   the gate is positioned to assist with switching between high and low conduction states associated with current flow between the first and second conductors through the NDR device.   
     
     
         18 . The semiconductor structure of  claim 16 , wherein the first and third diffusion regions are n-type regions and the second and fourth diffusion regions are p-type regions. 
     
     
         19 . A memory cell, comprising:
 a semiconductor substrate with diffusion regions adapted to provide a negative differential resistance (NDR) response, the diffusion regions including a first diffusion region, a second diffusion region, a third diffusion region and a fourth diffusion region, the first and third diffusion regions of a first type, the second and fourth diffusion regions of a second type, the second diffusion region positioned between the first diffusion region and the third diffusion region, and the third diffusion region positioned between the second diffusion region and the fourth diffusion region;   a gate separated from the second diffusion region by a gate insulator;   a first conductor line connected to the first diffusion region;   a second conductor line connected to the fourth diffusion region;   a third conductor line connected to the gate;   an access transistor, wherein the access transistor includes the first, second and third diffusion regions, the gate and the gate insulator; and   a diode, wherein the diode includes the third and fourth diffusion regions,   wherein the first diffusion region is an n+ region, the second diffusion region is a p− region, the third diffusion region is a n+ region, and the fourth diffusion region is a p+ region, and wherein the memory cell is adapted to conduct charge between the first and second conductor lines through the first, second, third and fourth diffusion regions.   
     
     
         20 . The memory cell of  claim 19 , wherein the p− region is adapted to function as a transistor body region and the n+ regions are adapted to function as transistor source/drain regions.