Phase detecting circuit and pll circuit

Abstract

A phase detecting circuit includes a latch circuit that switches, based on an OR signal and an NAND signal of two clock signals to be subjected to phase comparison, one of outputs used for generation of two pulse signals on an advance phase side and a delay phase side to a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and holds the output in the states.

1 . A phase detecting circuit comprising:
 a latch circuit configured to switch, based on an OR signal and a NAND signal of two clock signals wherein the two clock signals are subjected to phase comparison, an output of the latch circuit configured to be used for generating two pulse signals on an advance phase side and a delay phase side, the output configured to switch between a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and configured to hold the output in the states;   a first input circuit comprising first and second duty adjusting circuits configured to respectively adjust duties of the two clock signals, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit;   a second input circuit configured to output a NAND signal of the two clock signals to the other input terminal of the latch circuit; and   an output circuit configured to output the two pulse signals based on the one output of the latch circuit and the two clock signals.   
     
     
         2 . The phase detecting circuit according to  claim 1 , wherein
 the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and   the phase detecting circuit further comprises:   first and second duty adjusting circuits configured to respectively adjust duties of the two clock signals;   first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits;   a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit;   a fourth NAND circuit configured to output a NAND signal of the two clock signals to the other input terminal of the second NAND circuit;   a third inverter configured to logically invert and output an output of the second NAND circuit; and   first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the two clock signals corresponding thereto.   
     
     
         3 . The phase detecting circuit according to  claim 1 , wherein
 the first and second duty adjusting circuits are configured to respectively adjust, with a serial circuit of two or more inverters, duties of the two clock signals, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit.   
     
     
         4 . The phase detecting circuit according to  claim 1 , wherein
 the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and   the phase detecting circuit further comprises:   first and second duty adjusting circuits configured to respectively adjust, with serial inverters in two stages, duties of the two clock signals;   first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits;   a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit;   a fourth NAND circuit configured to output a NAND signal of the two clock signals to the other input terminal of the second NAND circuit;   a third inverter configured to logically invert and output an output of the second NAND circuit; and   first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the two clock signals corresponding thereto.   
     
     
         5 . A PLL circuit comprising:
 a phase detecting circuit comprising a latch circuit configured to switch, based on an OR signal and a NAND signal of a reference clock signal wherein the reference clock signal is subjected to phase comparison and a frequency-divided clock signal obtained by frequency-dividing a system clock signal, an output of the latch circuit configured to be used for generating two pulse signals on an advance phase side and a delay phase side, the output configured to switch between a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and configured to hold the output in the states;   a charge pump circuit configured to supply an electric current corresponding to pulse widths of the two pulse signals;   a loop filter configured to convert the electric current from the charge pump circuit into a control voltage signal; and   a voltage control oscillation circuit configured to generate the system clock signal having a frequency corresponding to a potential of the control voltage signal,   wherein the phase detecting circuit further comprises   a first input circuit comprising first and second duty adjusting circuits configured to respectively adjust duties of the reference clock signal and the system clock signal, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit;   a second input circuit configured to output a NAND signal of the reference clock signal and the system clock signal to the other input terminal of the latch circuit; and   an output circuit configured to output the two pulse signals based on the output of the latch circuit and the reference clock signal and the system clock signal.   
     
     
         6 . The PLL circuit according to  claim 5 , wherein
 in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and   the phase detecting circuit further comprises   first and second duty adjusting circuits that respectively adjust duties of the reference clock signal and the system clock signal;   first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits;   a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit;   a fourth NAND circuit configured to output a NAND signal of the reference clock signal and the system clock signal to the other input terminal of the second NAND circuit;   a third inverter configured to logically invert and output an output of the second NAND circuit; and   first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the reference clock signal and the system clock signal corresponding thereto.   
     
     
         7 . The PLL circuit according to  claim 5 , wherein the phase detecting circuit comprises:
 the first and second duty adjusting circuits are configured to respectively adjust, with a serial circuit of two or more inverters, duties of the reference clock signal and the system clock signal, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit.   
     
     
         8 . The PLL circuit according to  claim 5 , wherein
 in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and   the phase detecting circuit further comprises:   first and second duty adjusting circuits configured to respectively adjust, with serial inverters in two stages, duties of the reference clock signal and the system clock signal;   first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits;   a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit;   a fourth NAND circuit configured to output a NAND signal of the reference clock signal and the system clock signal to the other input terminal of the second NAND circuit;   a third inverter configured to logically invert and output an output of the second NAND circuit; and   first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the reference clock signal and the system clock signal corresponding thereto.   
     
     
         9 . A PLL circuit comprising:
 a first frequency dividing circuit configured to frequency-divide a reference clock signal;   a second frequency dividing circuit configured to frequency-divide a frequency-divided clock signal obtained by frequency-dividing a system clock signal;   a phase detecting circuit comprising a latch circuit configured to switch, based on an OR signal and a NAND signal of an output of the first frequency dividing circuit and an output of the second frequency dividing circuit wherein the output of the first frequency dividing circuit and the output of the second frequency dividing circuit are subjected to phase comparison, an output of the phase detecting circuit configured to be used for generating two pulse signals on an advance phase side and a delay phase side, the output configured to switch between a preparation operation state for performing the phase comparison and a circuit operation state after the phase comparison, and configured to hold the output in the states;   a charge pump circuit configured to supply an electric current corresponding to pulse widths of the two pulse signals;   a loop filter configured to convert the electric current from the charge pump circuit into a control voltage signal; and   a voltage control oscillation circuit configured to generate the system clock signal having a frequency corresponding to potential of the control voltage signal.   
     
     
         10 . The PLL circuit according to  claim 9 , wherein
 the phase detecting circuit comprises:   a first input circuit comprises first and second duty adjusting circuits configured to respectively adjust outputs of the first and second frequency dividing circuits, and output an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit;   a second input circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the latch circuit; and   an output circuit configured to output the two pulse signals based on the one output of the latch circuit and the outputs of the first and second frequency dividing circuits.   
     
     
         11 . The PLL circuit according to  claim 9 , wherein
 in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and   the phase detecting circuit further comprises:   first and second duty adjusting circuits configured to respectively adjust duties of the outputs of the first and second frequency dividing circuits;   first and second inverters configured to respectively logically invert and output the outputs of the first and second frequency dividing circuits corresponding thereto;   a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit;   a fourth NAND circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the second NAND circuit;   a third inverter configured to logically invert and output an output of the second NAND circuit; and   first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and the outputs of the first and second frequency dividing circuits corresponding thereto.   
     
     
         12 . The PLL circuit according to  claim 9 , wherein
 the phase detecting circuit further comprises:   a first input circuit comprises first and second duty adjusting circuits configured to respectively adjust, with a series circuit of two or more inverters, duties of the outputs of the first and second frequency dividing circuits, and outputs an OR signal of outputs of the first and second duty adjusting circuits to one input terminal of the latch circuit;   a second input circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the latch circuit; and   an output circuit configured to output the two pulse signals based on the one output of the latch circuit and the outputs of the first and second frequency dividing circuits.   
     
     
         13 . The PLL circuit according to  claim 9 , wherein
 in the phase detecting circuit, the latch circuit comprises first and second NAND circuits, wherein input terminals and output terminals of the first and second NAND circuits are respectively cross-connected, and   the phase detecting circuit further comprises:   first and second duty adjusting circuits configured to respectively adjust, with serial inverters in two stages, duties of the outputs of the first and second frequency dividing circuits;   first and second inverters configured to respectively logically invert and output outputs corresponding thereto of the first and second duty adjusting circuits;   a third NAND circuit configured to output a NAND signal of outputs of the first and second inverters to the other input terminal of the first NAND circuit;   a fourth NAND circuit configured to output a NAND signal of the outputs of the first and second frequency dividing circuits to the other input terminal of the second NAND circuit;   a third inverter configured to logically invert and output an output of the second NAND circuit; and   first and second AND circuits configured to respectively output, as the two pulse signals corresponding thereto, AND signals of an output of the third inverter and output signals corresponding thereto of the first and second frequency dividing circuits.