Semiconductor device having insulated gate field effect transistors and method of manufacturing the same
Abstract
N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers.
Claims
exact text as granted — not AI-modified1 .- 9 . (canceled)
10 . A method of manufacturing a semiconductor device, comprising:
providing an N-type semiconductor region and a P-type semiconductor region in a surface region of a semiconductor substrate; forming an insulating film to be a gate insulating film on the semiconductor substrate; forming a silicon containing film on the insulating film; introducing P-type impurities into a first portion of the silicon containing film above the N-type semiconductor region, etching and thinning the first portion of the silicon containing film in a thickness direction of the first portion and introducing N-type impurities into a second portion of the silicon containing film above the P-type semiconductor region; providing an etching mask having first and second patterns on the silicon containing film to position the first and second patterns of the etching mask corresponding to gate electrode patterns above the thinned first and second portions of the silicon containing film respectively, and etching the thinned first and second portions together to form gate electrode films above the N-type and P-type semiconductor regions respectively; introducing P-type impurities into the N-type semiconductor region using the gate electrode film located above the N-type semiconductor region as a mask so as to form P-type source and drain layers in the N-type semiconductor region and introducing N-type impurities into the P-type semiconductor region using the gate electrode film located above the P-type semiconductor region as a mask so as to form N-type source and drain layers in the P-type semiconductor region.
11 . A method of manufacturing a semiconductor device, according to claim 10 ,
wherein etching of the thinned first portion and the second portion of the silicon containing film and to be etched in the thickness direction is ended in the same time period substantially in forming the gate electrode films.
12 . A method of manufacturing a semiconductor device according to claim 10 , further comprising:
forming a first conductive film on the insulating film above the N-type semiconductor region after the insulating film is formed and before the silicon containing film is formed, the first conductive film being composed of a material different from that of the silicon containing film and being etched together with the thinned first portion of the silicon containing film to be processed to form the gate electrode film above the N-type semiconductor region.
13 . A method of manufacturing a semiconductor device according to claim 12 , further comprising:
forming a second conductive film on the insulating film above the P-type semiconductor region after the insulating film is formed and before the silicon containing film is formed, the second conductive film being composed of a material different from that of the silicon containing film and being etched together with the second portion of the silicon containing film to be processed to form the gate electrode film above the P-type semiconductor region.
14 . A method of manufacturing a semiconductor device according to claim 13 ,
wherein the first and second conductive films are a film composed of at least one selected from a metal film, a metal nitride film, a metal silicide film or a metal carbide film.
15 . A method of manufacturing a semiconductor device according to claim 14 ,
wherein the first and second conductive films are composed of different materials.
16 . A method of manufacturing a semiconductor device according to claim 14 ,
wherein the first and second conductive films have the same thickness approximately.
17 . A method of manufacturing a semiconductor device, comprising:
providing an N-type semiconductor region and a P-type semiconductor region in a surface region of a semiconductor substrate; forming an insulating film to be a gate insulating film on the semiconductor substrate; forming a first silicon containing film on the insulating film; introducing P-type impurities into a first portion of the first silicon containing film above the N-type semiconductor region, forming a protection film on the first portion of the first silicon containing film selectively, forming a second silicon containing film covering the protection film and a second portion of the first silicon containing film above the P-type semiconductor region, polishing and flattening the second silicon containing film to leave the second silicon containing film partially above the second portion of the first silicon containing film so as to form a laminated silicon containing film and introducing N-type impurities into at least one of the second portion of the first silicon containing film and the remaining second silicon containing film; providing an etching mask having first and second patterns corresponding to gate electrode patterns to position the first and second patterns on the first portion of the first silicon containing film and the laminated silicon containing film respectively, and etching the first portion of the first silicon containing film and the laminated silicon containing film together to form gate electrode films above the N-type and P-type semiconductor regions respectively; introducing P-type impurities into the N-type semiconductor region using the gate electrode film located above the N-type semiconductor region as a mask so as to form P-type source and drain layers in the N-type semiconductor region and introducing N-type impurities into the P-type semiconductor region using the gate electrode film located above the P-type semiconductor region as a mask so as to form N-type source and drain layers in the P-type semiconductor region.
18 . A method of manufacturing a semiconductor device, according to claim 17 ,
wherein etching of the first portion of the silicon containing film and the laminated silicon containing film in the thickness direction is ended in the same time period substantially in forming the gate electrode films.
19 . A method of manufacturing a semiconductor device according to claim 17 , further comprising:
forming a first conductive film on the insulating film above the N-type semiconductor region after the insulating film is formed and before the first silicon containing film is formed, the first conductive film being composed of a material different from that of the first silicon containing film and being etched together with the first portion of the first silicon containing film to be processed to form the gate electrode film above the N-type semiconductor region.
20 . A method of manufacturing a semiconductor device according to claim 17 , further comprising:
forming a second conductive film on the insulating film above the P-type semiconductor region after the insulating film is formed and before the first silicon containing film is formed, the second conductive film being composed of a material different from that of the first silicon containing film and being etched together with the laminated silicon containing film to be processed to form the gate electrode film above the P-type semiconductor region.Join the waitlist — get patent alerts
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