Non-Volatile Memory Device

Abstract

A non-volatile memory device includes memory cell active regions and common source active regions extending in parallel on a semiconductor substrate, a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions, word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions, and memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions, wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate.

1 . A non-volatile memory device comprising:
 memory cell active regions and common source active regions extending in parallel on a semiconductor substrate;   a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions;   word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions; and   memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions,   wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate.   
     
     
         2 . The non-volatile memory device of  claim 1 , wherein the memory cell active regions and the common source active regions extend in a first direction, and
 the self aligned source active region and the word lines extend in a second direction perpendicular to the first direction.   
     
     
         3 . The non-volatile memory device of  claim 1 , wherein the semiconductor substrate is of a first conductive type,
 the source and drain regions of each of the common source line transistors are of a second conductive type, and further comprising   a channel region of the first conductive type between the source and drain regions of each of the common source line transistors.   
     
     
         4 . The non-volatile memory device of  claim 3 , wherein the first conductive type is a P type, and the second conductive type is an N type. 
     
     
         5 . The non-volatile memory device of  claim 1 , further comprising at least two common source active regions adjacent to each other on the substrate. 
     
     
         6 . The non-volatile memory device of  claim 1 , wherein a distance between the source and drain regions of the common source line transistors is less than a distance between source and drain regions of the memory cell transistors. 
     
     
         7 . The non-volatile memory device of  claim 1 , wherein an effective channel length of the common source line transistors is less than an effective channel length of the memory cell transistors. 
     
     
         8 . The non-volatile memory device of  claim 1 , wherein the non-volatile memory device includes a NOR flash memory device. 
     
     
         9 . A non-volatile memory device comprising:
 memory cell active regions and common source active regions extending in parallel on a semiconductor substrate;   a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions;   word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions; and   memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions,   wherein the common source line transistors and the memory cell transistors are enhancement type transistors.   
     
     
         10 . The non-volatile memory device of  claim 9 , wherein the common source line transistors and the memory cell transistors are electrically isolated while no bias voltage is applied to the word lines. 
     
     
         11 . The non-volatile memory device of  claim 9 , wherein a threshold voltage of the common source line transistors and the memory cell transistors is greater than 0 V. 
     
     
         12 . The non-volatile memory device of  claim 9 , further comprising at least two common source active regions adjacent to each other on the substrate. 
     
     
         13 . The non-volatile memory device of  claim 11 , wherein while no bias voltage is applied to the word lines, no source voltage is applied through the common source line transistors, and the source regions of each of the memory cell transistors are floating, and
 when the bias voltage is applied to the word lines, the source voltage is applied to the source region of each of the memory cell transistors through the common source line transistors.   
     
     
         14 . A non-volatile memory device comprising:
 memory cell active regions and common source active regions extending in parallel on a semiconductor substrate;   a self aligned source active region disposed on the semiconductor substrate extending perpendicular to the memory cell active regions and the common source active regions and that connects the memory cell active regions to the common source active regions;   word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions; and   memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions,   wherein while no bias voltage is applied to the word lines, no source voltage is applied through the common source line transistors, and when the bias voltage is applied to the word lines, the source voltage is applied to the source region of each of the memory cell transistors through the common source line transistors.   
     
     
         15 . The non-volatile memory device of  claim 14 , wherein while no bias voltage is applied to the word lines, the common source line transistors and the memory cell transistors are electrically isolated and the source regions of each of the memory cell transistors are floating. 
     
     
         16 . The non-volatile memory device of  claim 14 , wherein a threshold voltage of the common source line transistors and the memory cell transistors is greater than 0 V. 
     
     
         17 . The non-volatile memory device of  claim 14 , wherein the semiconductor substrate is of a first conductive type,
 source and drain regions of each of the common source line transistors are of a second conductive type, and further comprising   a channel region of the first conductive type between the source and drain regions of each of the common source line transistors.   
     
     
         18 . The non-volatile memory device of  claim 14 , further comprising at least two common source active regions adjacent to each other on the substrate. 
     
     
         19 . The non-volatile memory device of  claim 14 , wherein a distance between source and drain regions of the common source line transistors is less than a distance between source and drain regions of the memory cell transistors. 
     
     
         20 . The non-volatile memory device of  claim 1 , wherein an effective channel length of the common source line transistors is less than an effective channel length of the memory cell transistors.