Scalable flash eeprom memory cell with floating gate spacer wrapped by control gate and method of manufacture

Abstract

A flash memory cell includes a substrate having a surface region and a flash memory cell structure on the surface region. The flash memory cell structure includes a gate dielectric layer on the surface region, a select gate on the gate dielectric layer, a cap oxide layer on the select gate, an oxide spacer on a first edge of the select gate, a tunnel oxide layer on a first region and on a second region of the surface region. The second region is an active region. The flash memory cell structure further includes a poly spacer on the first edge of the oxide spacer and a portion of the tunnel oxide layer on the first region, an ONO layer on at least the poly spacer and a control gate layer on the ONO layer.

1 . A flash memory cell comprising:
 a substrate having a surface region;   a flash memory cell structure overlying the surface region, the flash memory cell structure comprising:
 a gate dielectric layer overlying the surface region; 
 a select gate overlying the gate dielectric layer; 
 a cap oxide layer overlying the select gate; 
 an oxide spacer formed overlying a first edge of the select gate; 
 a tunnel oxide layer formed overlying a first region of the surface region and formed overlying a second region of the surface region, wherein the second region is an active region; 
 a poly spacer formed overlying the oxide spacer on the first edge and a portion of the tunnel oxide layer overlying the first region; 
 an ONO layer overlying at least the poly spacer; and 
 a control gate layer overlying the ONO layer. 
   
     
     
         2 . The flash memory cell of  claim 1 , wherein the cap oxide layer is about 1000 Angstroms and less. 
     
     
         3 . The flash memory cell of  claim 1 , wherein the oxide spacer has a thickness of about 300 Angstroms and less. 
     
     
         4 . The flash memory cell of  claim 1 , wherein the poly spacer has a thickness of about 1000 Angstroms and less and forms a floating gate structure. 
     
     
         5 . The flash memory cell of  claim 1 , wherein the substrate comprises silicon. 
     
     
         6 . The flash memory cell of  claim 1 , wherein the select gate has a channel length of 0.13 micron and less.