Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits

Abstract

Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

1 . A buffering system for non-volatile memory, comprising:
 a plurality of memory layers that are vertically stacked upon one another and divided into partitions, each memory layer is in direct contact with an adjacent memory layer;   a plurality of memory elements included in each memory layer, each memory element having exactly two terminals and including an ion reservoir and a tunnel barrier electrically in series with each other and with the two terminals;   a logic layer fabricated on a silicon substrate and including circuitry electrically coupled with the plurality of memory elements in the plurality of memory layers, the plurality of memory layers are integrally fabricated directly on top of and in direct contact with the silicon substrate;   at least one write buffer configured to facilitate writing to a first subset of partitions during a write cycle; and   a write override circuit included in the circuitry and including a comparator electrically coupled with the write buffer and a read-before-write buffer electrically coupled with sense amp circuitry and the comparator, wherein during a first phase of a write cycle the sense amp circuitry communicates read data from at least one memory element to be written to during the write cycle to the read-before-write buffer, and during a second phase of the write cycle the comparator compares the read data with write data stored in the write buffer and generates a data miscompare signal if the read data and the write data are different, the data miscompare signal operative to allow the write data to be written to the at least one memory element.   
     
     
         2 . The buffering system of  claim 1  and further comprising:
 at least one read buffer configured to facilitate reading from a second subset of partitions during a read cycle, wherein the at least one read buffer is sized differently than the at least one write buffer. 
 
     
     
         3 . The buffering system of  claim 1 , wherein each memory element changes its conductivity profile as a function of a voltage differential applied across its two terminals. 
     
     
         4 . The buffering system of  claim 3 , wherein the circuitry includes a variable programmer circuit configured to generate the voltage differential in accordance with a slew rate. 
     
     
         5 . The buffering system of  claim 4 , wherein the variable programmer circuit is configured to generate the voltage differential in the first phase and the second phase of the write cycle. 
     
     
         6 . The buffering system of  claim 1 , wherein the circuitry includes an interface configured to transmit data in accordance with an interface rate to the at least one write buffer, and wherein the at least one write buffer is configured to alternately load data at the interface rate and to write data at a write speed that is substantially the same as the interface rate. 
     
     
         7 . The buffering system of  claim 6 , wherein the interface further comprises either a NOR-type interface or a NAND-type interface. 
     
     
         8 . The buffering system of  claim 1 , wherein the at least one write buffer is configured to write a specific number of bits during the write cycle and the specific number of bits are selected to perform the write cycle at a peak power that does not exceed a peak power threshold. 
     
     
         9 . The buffering system of  claim 1 , wherein the write override circuit is configured to prevent writing to one or more memory elements in the plurality of memory layers when the data to be written to the one or more memory elements is identical to the read data stored in the read-before-write buffer. 
     
     
         10 . The buffering system of  claim 1  wherein one or more of the plurality of memory layers includes the at least one write buffer. 
     
     
         11 . The buffering system of  claim 1 , wherein each memory element is re-writable, stores at least one bit of data, and retains the data in an absence of electrical power. 
     
     
         12 . The buffering system of  claim 1 , wherein the circuitry includes a variable programming circuit configured to vary a programming characteristic for programming the one or more portions of the plurality of memory layers. 
     
     
         13 . The buffering system of  claim 12 , wherein the at least one write buffer is configured to include an amount of data bits as a function of a rate of change of the programming characteristic. 
     
     
         14 . The buffering system of  claim 1 , wherein the circuitry includes a buffer controller configured to synchronize during an interval the loading of data into a first write buffer and the writing of data from a second write buffer. 
     
     
         15 . The buffering system of  claim 1 , wherein the circuitry includes the at least one write buffer. 
     
     
         16 . The buffering system of  claim 1  and further comprising:
 at least one read buffer included in the circuitry and configured to facilitate reading from a second subset of partitions during a read cycle, wherein the at least one read buffer is sized differently than the at least one write buffer. 
 
     
     
         17 . The buffering system of  claim 1  and further comprising:
 at least one read buffer included in one or more of the plurality of memory layers and configured to facilitate reading from a second subset of partitions during a read cycle, wherein the at least one read buffer is sized differently than the at least one write buffer. 
 
     
     
         18 . The buffering system of  claim 1 , wherein the ion reservoir includes mobile oxygen ions and the tunnel barrier is made from a material that is an electrolyte to the mobile oxygen ions and is configured for electron tunneling during data operations to the memory element. 
     
     
         19 . The buffering system of  claim 18 , wherein a programming operation is operative to transport a portion of the mobile oxygen ions from the ion reservoir and into the tunnel barrier to store data as a programmed state. 
     
     
         20 . The buffering system of  claim 18 , wherein an erase operation is operative to transport mobile oxygen ions that were previously transported to the tunnel barrier back into the ion reservoir to store data as an erased state.