Bus systems and methods for controlling data flow in a field of processing elements

Abstract

A bus system for a configurable architecture and methods therefor are provided in which optimization of the configuration efficiency and reconfiguration efficiency are taken into account separately. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a data packet conditional upon and/or responsive to the second hardware element's assignment of a signal to a connecting bus via which the data packet is transmitted, where the signal indicates that no incoming data packet can be lost. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a first data packet and subsequently a second data packet; and receiving, by the first hardware element and from the second hardware element, an acknowledgement of the first data packet subsequent to the transmittal of the second data packet.

1 - 8 . (canceled) 
     
     
         9 . A data transmission controlling method comprising:
 transmitting, by a first hardware element and to a second hardware element, a data packet at least one of conditional upon and responsive to the second hardware element assigning a signal to a connecting bus via which the data packet is transmitted, the signal indicating that no incoming data packet can be lost.   
     
     
         10 . A data transmission controlling method, comprising:
 transmitting, by a first hardware element and to a second hardware element, a first data packet and subsequently a second data packet; and   receiving, by the first hardware element and from the second hardware element, an acknowledgement of the first data packet subsequent to the transmittal of the second data packet.