Test mask set and mask set

Abstract

A test mask set includes a first test mask having a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns; and a second test mask having a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns. The gate patterns formed in different areas among the plurality of gate pattern areas differ in at least one of a gate spacing or a gate width. The active patterns formed in different areas among the plurality of active pattern areas differ in at least one of an active spacing or an active width

1 . A test mask set comprising:
 a first test mask having a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns; and   a second test mask having a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns,   wherein the gate patterns formed in different areas among the plurality of gate pattern areas differ in at least one of a gate spacing or a gate width, and   the active patterns formed in different areas among the plurality of active pattern areas differ in at least one of an active spacing or an active width.   
     
     
         2 . The test mask set as claimed in  claim 1 , wherein:
 the gate pattern areas are disposed in parallel with each other in a first direction, and   the active pattern areas are disposed in parallel with each other in a second direction.   
     
     
         3 . The test mask set as claimed in  claim 2 , wherein the first direction and the second direction are perpendicular to each other. 
     
     
         4 . The test mask set as claimed in  claim 2 , wherein the plurality of gate pattern areas and the plurality of active pattern areas are disposed to overlap each other in a grid configuration. 
     
     
         5 . The test mask set as claimed in  claim 1 , wherein the gate width is in a range of about 0.03 μm to about 10 μm. 
     
     
         6 . The test mask set as claimed in  claim 5 , wherein the active width is in a range of about 0.06 μm to about 10 μm. 
     
     
         7 . The test mask set as claimed in  claim 1 , wherein the gate patterns are configured to form a gate electrode using a CMP process. 
     
     
         8 . The test mask set as claimed in  claim 7 , wherein the gate patterns are configured to define an area where the gate electrode is to be formed by etching an interlayer dielectric film. 
     
     
         9 . The test mask set as claimed in  claim 1 , wherein densities of the gate patterns formed in different gate pattern areas differ from each other. 
     
     
         10 . The test mask set as claimed in  claim 1 , further comprising a third test mask having an area with a booster disposed therein and an area without a booster. 
     
     
         11 . A test mask set comprising:
 a first test mask having a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern formed therein, the first gate pattern having a first gate spacing and a first gate width, the second gate pattern having the first gate spacing and a second gate width, the second gate width being different from the first gate width, the third gate pattern having a second gate spacing, the second gate spacing being different from the first gate spacing, and the first gate width, and the fourth gate pattern having the second gate spacing and the second gate width; and   a second test mask having a first active pattern, a second active pattern, a third active pattern and a fourth active pattern formed therein, the first active pattern having a first active spacing and a first active width, the second active pattern having the first active spacing and a second active width, the second active width being different from the first active width, the third active pattern having a second active spacing, the second active spacing being different from the first active spacing, and the first active width, and the fourth active pattern having the second active spacing and the second active width.   
     
     
         12 . The test mask set as claimed in  claim 11 , wherein the first to fourth gate patterns and the first to fourth active patterns are disposed to overlap each other in a grid configuration. 
     
     
         13 . The test mask set as claimed in  claim 11 , further comprising a third test mask having an area with a booster and an area without a booster. 
     
     
         14 . A mask set comprising:
 a first mask having a first pattern area and a first test area disposed therein; and   a second mask having a second pattern area and a second test area disposed therein,   wherein:   the first test area has a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns formed therein, the gate patterns formed in different areas among the plurality of gate pattern areas differing in at least one of a gate spacing or a gate width; and   the second test area has a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns formed therein, the active patterns formed in different areas among the plurality of active pattern areas differing in at least one of an active spacing or an active width.   
     
     
         15 . The mask set as claimed in  claim 14 , wherein:
 the gate pattern areas are disposed in parallel with each other in a first direction, and   the active pattern areas are disposed in parallel with each other in a second direction.   
     
     
         16 . The mask set as claimed in  claim 15 , wherein the first direction and the second direction are perpendicular to each other. 
     
     
         17 . The mask set as claimed in  claim 15 , wherein the plurality of gate pattern areas and the plurality of active pattern areas are disposed to overlap each other in a grid configuration. 
     
     
         18 . The mask set as claimed in  claim 14 , wherein the gate patterns are configured to form a gate electrode using a CMP process. 
     
     
         19 . The mask set as claimed in  claim 14 , wherein densities of the gate patterns formed in different gate pattern areas differ from each other. 
     
     
         20 . The mask set as claimed in  claim 14 , further comprising a third test mask having an area with a booster and an area without a booster.