Semiconductor device with buried gate and method for fabricating the same

Abstract

A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.

1 . A semiconductor device, comprising:
 buried gates formed over a substrate;   storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern; and   a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the pillar pattern corresponds to a region where the storage node contact plugs are to be formed, and the line pattern isolated by bit line structure. 
     
     
         3 . The semiconductor device of  claim 1 , wherein lines of the line pattern each extend in a direction parallel to a direction that the buried gates between the buried gates extend. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the bit line structure comprises:
 a line-type damascene pattern penetrating an inter-layer dielectric layer formed over the substrate;   bit line spacers formed on the sidewalls of the damascene pattern;   bit lines filling a portion of the damascene pattern; and   a bit line sealing layer filling the remaining portion of the damascene pattern.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the line-type damascene pattern crosses the buried gates. 
     
     
         6 . A method for fabricating a semiconductor device, comprising:
 forming a first layer over a substrate;   forming a first pattern which exposes the substrate by selectively etching the first layer;   forming a second layer to cover the substrate;   forming a line-type second pattern coupled with the first pattern by selectively etching the second layer;   forming a conductive layer to fill the first pattern and the second pattern; and   forming contact plugs by selectively etching the conductive layer.   
     
     
         7 . The method of  claim 6 , wherein the first pattern is formed as a hole type that opens regions of the substrate where the contact plugs are to be formed. 
     
     
         8 . The method of  claim 6 , wherein the first pattern is formed as a bar type that opens regions of the substrate where the contact plugs are to be formed and respective adjacent regions. 
     
     
         9 . The method of  claim 6 , wherein the forming of the contact plugs comprises:
 forming a line pattern by selectively etching the first layer, the second layer, and the conductive layer.   
     
     
         10 . The method of  claim 9 , wherein the line pattern crosses the second pattern. 
     
     
         11 . A method for fabricating a semiconductor device, comprising:
 forming buried gates over a substrate;   forming a first layer over the substrate;   forming a first pattern by selectively etching the first layer;   forming a second layer over the substrate including the first pattern;   forming a line-type second pattern coupled with the first pattern and selectively etching the second layer;   forming a conductive layer that fills storage node contact holes including the first pattern and the second pattern; and   forming storage node contact plugs by selectively etching the conductive layer, the second layer, and the first layer to form a damascene pattern simultaneously.   
     
     
         12 . The method of  claim 11 , further comprising:
 forming bit line spacers on sidewalls of the damascene pattern;   forming bit lines filling a portion of the damascene pattern; and   forming a bit line sealing layer over the bit lines to fill the remaining portion of the damascene pattern.   
     
     
         13 . The method of  claim 11 , wherein the first pattern is formed as a hole type that exposes regions of the substrate where the storage node contact plugs are to be formed. 
     
     
         14 . The method of  claim 11 , wherein the first pattern is formed as a bar type that opens regions of the substrate where the storage node contact plugs are to be formed and respective adjacent regions. 
     
     
         15 . The method of  claim 11 , wherein the forming of the first pattern comprises:
 forming a photoresist layer pattern over the first layer to cover a region where the bit lines are to be formed; and   performing a blanket etch process by using the photoresist layer pattern until the substrate is exposed.   
     
     
         16 . The method of  claim 11 , wherein lines of the second pattern is formed to each extend in a direction parallel to a direction that the buried gates extend. 
     
     
         17 . The method of  claim 11 , wherein the forming of the line-type second pattern coupled with the first pattern includes stopping an etch process at the second layer to obtain the second pattern and selectively removing the second layer using the second pattern. 
     
     
         18 . The method of  claim 11 , wherein the first layer comprises a nitride layer and the second layer comprises an oxide layer. 
     
     
         19 . The method of  claim 11 , wherein the damascene pattern is formed as a line pattern extended in a direction crossing the buried gates and the second pattern. 
     
     
         20 . The method of  claim 11 , wherein the second layer is formed to occupy a same space outlining the first pattern before the selective etching of the first layer. 
     
     
         21 . The method of  claim 11 , further comprising forming a bit line structure including a bit line in the damascene pattern, wherein the first layer remains in a region of the substrate over which the bit line structure is to be formed after the selective etching of the first layer. 
     
     
         22 . The method of  claim 11 , further comprising forming landing plugs located under the storage node contact plugs, respectively, wherein the landing plugs each have a width narrower than a width of the respective storage node contact plug. 
     
     
         23 . The method of  claim 11 , further comprising forming an additional layer over the second layer to fill the first pattern and extend over the substrate obtained after the forming of the first pattern in height, wherein the forming of line-type second pattern includes etching the additional layer so that the second pattern and the first pattern combined creates an overall pattern deeper in depth than the etched depth of the substrate in the selective etching of the first layer.