Semiconductor device and method for manufacturing the same

Abstract

A method include disposing a semiconductor chip having an electrode pad formed on a circuit forming surface on one surface of a support so that the electrode pad contacts with the one surface of the support, forming a first insulating layer on the one surface of the support so that the first insulating layer covers at least a side surface of the semiconductor chip, removing the support and forming an interconnection terminal on the electrode pad, forming a second insulating layer on the circuit forming surface of the semiconductor chip and the first insulating layer so that the second insulating layer covers the interconnection terminal, exposing an end portion of the interconnection terminal from a top surface of the second insulating layer, and forming a wiring pattern that is electrically connected to the end portion of the interconnection terminal, on the top surface of the second insulating layer.

1 . A method for manufacturing a semiconductor device, comprising:
 a first process of disposing a semiconductor chip having an electrode pad formed on a circuit forming surface on one surface of a support so that the electrode pad contacts with the one surface of the support;   a second process of forming a first insulating layer on the one surface of the support so that the first insulating layer covers at least a side surface of the semiconductor chip, and has a first surface facing the one surface of the support;   a third process of removing the support and forming an interconnection terminal on the electrode pad;   a fourth process of forming a second insulating layer on the circuit forming surface of the semiconductor chip and the first insulating layer so that the second insulating layer covers the interconnection terminal and has a first surface facing the circuit forming surface of the semiconductor chip and the first insulating layer, and a second surface opposite to the first surface;   a fifth process of exposing an end portion of the interconnection terminal from the second surface of the second insulating layer; and   a sixth process of forming a wiring pattern that is electrically connected to the end portion of the interconnection terminal, on the second surface of the second insulating layer.   
     
     
         2 . The method of  claim 1 , wherein, in the second process, the first insulating layer is formed on the one surface of the support so as to cover the side surface and a rear surface of the semiconductor chip. 
     
     
         3 . The method of  claim 1 , further comprising:
 a seventh process of roughening the first surface of the first insulating layer after removing the support and before forming the interconnection terminal, in the third process.   
     
     
         4 . The method of  claim 1 , further comprising:
 an eighth process of roughening the second surface of the second insulating layer between the fifth process and the sixth process.   
     
     
         5 . The method of  claim 1 , wherein, in the fifth process, the end portion of the interconnection terminal is exposed from the second surface of the second insulating layer by pressing the second insulating layer from the second surface thereof so that the second surface of the second insulating layer is planarized and the end portion of the interconnection terminal is planarized. 
     
     
         6 . The method of  claim 1 , wherein the first insulating layer and the second insulating layer are formed of the same material. 
     
     
         7 . A semiconductor device, comprising:
 a semiconductor chip having an electrode pad formed on a circuit forming surface;   an interconnection terminal formed on the electrode pad;   a first insulating layer formed so as to cover a side surface of the semiconductor chip;   a second insulating layer formed on the circuit forming surface of the semiconductor chip and the first insulating layer so as to expose an end portion of the interconnection terminal and cover the other portions except the end portion, the second insulating layer having a first surface facing the circuit forming surface of the semiconductor chip and the first insulating layer and a second surface opposite to the first surface; and   a wiring pattern formed on the second surface of the second insulating layer and electrically connected with the end portion of the interconnection terminal.   
     
     
         8 . The semiconductor device of  claim 7 , further comprising:
 an external connection terminal formed on the wiring pattern,   wherein the external connection terminal is formed at a portion where the external connection terminal overlaps the first insulating layer when viewed from above.   
     
     
         9 . The semiconductor device of  claim 7 , wherein the first insulating layer and the second insulating layer are formed of the same material. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the first insulating layer is formed so as to cover the side surface and a rear surface of the semiconductor chip.