High speed FRAM

Abstract

A memory cell includes four transistors and two ferroelectric capacitors, wherein one of the two ferroelectric capacitors is positively polarized and another one of the two ferroelectric capacitors is negatively polarized for storing a non-inverting data and an inverting data, and a pair of access transistors is connected to the two ferroelectric capacitors, a pair of reset transistors is connected to the two ferroelectric capacitors, where a local bit line pair is connected to the pair of access transistors and a local sense amp is connected to the local bit line pair. By storing the non-inverting data and inverting data in the memory cell, there is no need to generate reference voltage when reading, which simplifies array configuration and enhances performance for reading and writing.

1 . A memory device, comprising:
 a memory cell including four transistors and two ferroelectric capacitors, wherein the memory cell includes a pair of access transistors connecting to the two ferroelectric capacitors which store a non-inverting data and an inverting data, a pair of reset transistors connecting to the two ferroelectric capacitors; and one of the two ferroelectric capacitors is positively polarized and another one of the two ferroelectric capacitors is negatively polarized for storing the non-inverting data and the inverting data; and a local bit line pair is connected to the pair of access transistors and a sense amp is connected to the local bit line pair.   
     
     
         2 . A memory device, comprising:
 a memory cell storing a non-inverting data and an inverting data, wherein the non-inverting data is stored in a first ferroelectric capacitor which is connected to a first access transistor and a first reset transistor; and the inverting data is stored in a second ferroelectric capacitor which is connected to a second access transistor and a second reset transistor; and a first local bit line is connected to the first access transistor and a second local bit line is connected to the second access transistor; and a sense amp is connected to the first local bit and the second local bit line; and one of the ferroelectric capacitors is positively polarized and another one of the ferroelectric capacitors is negatively polarized in order to store the non-inverting data and the inverting data.