Nonvolatile semiconductor storage device

Abstract

A nonvolatile semiconductor storage device storing plural data bits in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data. In a first write operation processing data in the first unit, logic of one of the higher-order and the lower-order bit is fixed, and two multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the memory cell in a pseudo binary state. In a second write operation processing data in a second unit larger than the first unit, plural input data bits in a multivalued state and parity data for error correction in the second unit are stored in the memory cell.

1 . A nonvolatile semiconductor storage device comprising:
 a memory cell having a physical quantity corresponding to a plurality of values in order to store a multi bit data by assigning the multi bit data having a higher-order bit selected from one bit in a unit and a lower-order bit selected from one bit in another unit of data to each value of the memory cell; and   a controlling circuit configured to fix logic of the higher-order bit or the lower-order bit in a first write operation that processes data in the unit, the controlling circuit assigns two pieces of the values that maximize the difference between the plurality of values in the first write operation, the controlling circuit makes the memory cell store one bit of input data in a pseudo binary value in a first write operation, the controlling circuit makes the memory cell store the multi bit data of input data in a multiple value in a second write operation that processes data larger than the unit, the controlling circuit makes the memory cell store parity data for error correction in the second write operation.   
     
     
         2 . The nonvolatile semiconductor storage device according to  claim 1 , further comprising:
 an address space in the second write operation is controlled as the pseudo binary value or the plurality of values,   wherein the controlling circuit is configured to make the memory cells store first flag data in a case that the memory cell is in the pseudo binary value,   the controlling circuit is configured to make the memory cells store second flag data in a case that the memory cell is in the plurality of values,   the controlling circuit is configured to permit data processing by both the first write operation and the second write operation in a case that neither the first flag data nor the second flag data is stored,   the controlling circuit is configured to permit data processing by the first write operation and to inhibit data processing by the second write operation in a case that the first flag data is stored and the second flag data is not stored, and   the controlling circuit is configured to inhibit both data processing by the first write operation and data processing by the second write operation in a case that the second flag data is stored and the first flag data is not stored.   
     
     
         3 . The nonvolatile semiconductor storage device according to  claim 2 , wherein in a case that data processing by the first write operation is performed, the controlling circuit is configured to read the first flag data and the second flag data corresponding to a designated address space, and if the controlling circuit determines that the designated address space is in the pseudo binary state, the controlling circuit performs data processing omitted writing of the first flag data. 
     
     
         4 . The nonvolatile semiconductor storage device according to  claim 2 , wherein the first flag data is stored in the memory cell that stores the parity data, and
 the second flag data is stored in the one memory cell as the pseudo binary state.   
     
     
         5 . The nonvolatile semiconductor storage device according to  claim 3 , wherein the first flag data is stored in the memory cell that stores the parity data, and
 the second flag data is stored in the one memory cell as the pseudo binary state.   
     
     
         6 . The nonvolatile semiconductor storage device according to  claim 2 , wherein in a case that the first flag data is stored, the controlling circuit is configured to read input data corresponding to an address space whose logic is not fixed. 
     
     
         7 . The nonvolatile semiconductor storage device according to  claim 3 , wherein in a case that the first flag data is stored, the controlling circuit is configured to read input data corresponding to an address space whose logic is not fixed. 
     
     
         8 . The nonvolatile semiconductor storage device according to  claim 4 , wherein in a case that the first flag data is stored, the controlling circuit is configured to read input data corresponding to an address space whose logic is not fixed. 
     
     
         9 . The nonvolatile semiconductor storage device according to  claim 5 , wherein in a case that the first flag data is stored, the controlling circuit is configured to read input data corresponding to an address space whose logic is not fixed.