Method and apparatus for efficiently processing data packets in a computer network

Abstract

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

1 . The network device of  claim 38  wherein the programmable processor is a RISC processor. 
     
     
         2 . The network device of  claim 38 , wherein the CAM is searched to determine forwarding information for the packet. 
     
     
         3 . (canceled) 
     
     
         4 . The network device of  claim 38 , wherein the integrated circuit further comprises a CAM lookup handler configured to submit a lookup request to the CAM using the lookup target stored in the at least one register in the plurality of registers. 
     
     
         5 . The network device of  claim 38 , wherein the integrated circuit further comprises a parameter memory handler, configured to access a set of parameters from a parameter memory. 
     
     
         6 . The network device of  claim 5 , wherein the set of parameters are selected from a group consisting of routing parameters and switching parameters. 
     
     
         7 . The network device of  claim 38 , wherein the integrated circuit is configured to perform packet processing using results of the lookup in the CAM. 
     
     
         8 . The network device of  claim 5 , wherein the integrated circuit is configured to perform packet processing using values of said set of parameters. 
     
     
         9 . The network device of  claim 38 , wherein the integrated circuit is further configured to identify a valid packet context. 
     
     
         10 . The network device of  claim 38 , wherein the integrated circuit is further configured to remove a VLAN tag from a header of the packet. 
     
     
         11 . The network device of  claim 10 , wherein the integrated circuit is further configured to copy said VLAN tag to a packet status word. 
     
     
         12 . The network device of  claim 38 , wherein the integrated circuit is further configured to perform type of service (TOS) field lookups. 
     
     
         13 . The network device of  claim 38 , wherein the programmable processor is configured to determine information for forwarding the packet based upon a header of the packet. 
     
     
         14 . (canceled) 
     
     
         15 . The network device of  claim 38 , further comprising:
 a media access controller (MAC) coupled with the integrated circuit; and   a register for storing a status bit, the status bit being set when a destination address (DA) specified in the packet matches a MAC address.   
     
     
         16 . The network device of  claim 15  further comprising a host interface circuit to a host central processing unit, wherein when the status bit is set, the packet is routed to the host central processing unit over the host interface circuit. 
     
     
         17 - 37 . (canceled) 
     
     
         38 . A network device comprising:
 a content addressable memory (CAM); and   an integrated circuit separate from the CAM, the integrated circuit comprising:
 a programmable processor comprising a plurality of registers and a random access memory (RAM), the programmable processor operating under control of a program; and 
   wherein the programmable processor is configured to form a lookup target in at least one register in the plurality of registers based upon contents of a packet received by the network device;   wherein the integrated circuit is configured to perform a lookup in the CAM using the lookup target;   wherein the CAM is separate from the programmable processor.   
     
     
         39 . The network device of  claim 38  wherein the programmable processor further comprises a unit configured to perform arithmetic or logic operations on one or more values stored in one or more registers from the plurality of registers to generate a result that is stored in the at least one register and used for performing a lookup in the CAM. 
     
     
         40 - 41 . (canceled) 
     
     
         42 . The network device of  claim 38  wherein the integrated circuit is an application specific integrated circuit (ASIC). 
     
     
         43 . The network device of  claim 38  wherein the integrated circuit is implemented in a programmable logic device. 
     
     
         44 . A system comprising:
 a content addressable memory (CAM); and   an integrated circuit separate from the CAM, the integrated circuit comprising:
 a programmable processor comprising a plurality of registers and an arithmetic logic unit (ALU); and 
   wherein the programmable processor is configured to form a lookup target in at least one register in the plurality of registers based upon contents of a packet received by the system;   wherein the integrated circuit is configured to perform a lookup in the CAM using the lookup target;   wherein the CAM is separate from the programmable processor.   
     
     
         45 . The system of  claim 44  wherein the programmable processor further comprises a register select block configured to choose a register from the plurality of registers whose contents are to be sent to the ALU as operands.