Semiconductor memory device and method of manufacturing the same

Abstract

Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug ( 104 ) formed inside a first contact hole ( 103 ) penetrating through a first interlayer insulating layer ( 102 ); a lower electrode ( 105 ) having a flat top surface and is thicker above the first interlayer insulating layer ( 102 ) than above the first contact plug ( 104 ); a variable resistance layer ( 106 ); and an upper electrode ( 107 ). The lower electrode ( 105 ), the variable resistance layer ( 106 ), and the upper electrode ( 107 ) compose a variable resistance element.

1 . A semiconductor memory device comprising:
 a semiconductor substrate;   a first conductive layer formed on said semiconductor substrate;   a first interlayer insulating layer formed on said semiconductor substrate so as to cover said first conductive layer;   a first contact hole penetrating through said first interlayer insulating layer down to said first conductive layer;   a first contact plug formed inside said first contact hole and having a top surface located lower than a top surface of said first interlayer insulating layer;   a lower electrode formed on said first interlayer insulating layer so as to cover said first contact plug and having a planarized top surface, said lower electrode being thicker above said first contact plug than above said first interlayer insulating layer;   a variable resistance layer formed on said lower electrode; and   an upper electrode formed on said variable resistance layer,   wherein said lower electrode, said variable resistance layer, and said upper electrode compose a variable resistance element, and   said variable resistance layer is composed of a first variable resistance layer comprising a transition metal oxide and a second variable resistance layer comprising a transition metal oxide having an oxygen content percentage higher than an oxygen content percentage of the transition metal oxide in said first variable resistance layer, said variable resistance layer being brought into a state to be ready to start resistance change, by locally short-circuiting part of said second variable resistance layer.   
     
     
         2 . The semiconductor memory device according to  claim 1 ,
 wherein said lower electrode is composed of a plurality of layers.   
     
     
         3 . The semiconductor memory device according to  claim 2 ,
 wherein said lower electrode includes:   a first lower electrode; and   a second lower electrode provided on said first lower electrode,   a top surface of said first lower electrode above said first contact plug is lower than above said first interlayer insulating layer, and   said second lower electrode has a planarized top surface and is thicker above said first contact plug than above said first interlayer insulating layer.   
     
     
         4 . The semiconductor memory device according to  claim 2 ,
 wherein said lower electrode includes:   a first lower electrode; and   a second lower electrode provided on said first lower electrode,   said first lower electrode has a planarized top surface and is thicker above said first contact plug than above said first interlayer insulating layer, and   said second lower electrode is as thick above said first contact plug as above said first interlayer insulating layer.   
     
     
         5 . A method of manufacturing a semiconductor memory device which includes a variable resistance element composed of:
 a lower electrode;   a variable resistance layer formed on the lower electrode and including a first variable resistance layer comprising a transition metal oxide and a second variable resistance layer comprising a transition metal oxide having an oxygen content percentage higher than an oxygen content percentage of the transition metal oxide in the first variable resistance layer; and   an upper electrode formed on the variable resistance layer,   said method comprising:   forming a first lower conductive layer on a semiconductor substrate;   forming a first interlayer insulating layer on the semiconductor substrate so as to cover the first conductive layer;   forming a first contact hole penetrating through the first interlayer insulating layer down to the first conductive layer;   forming a first contact plug inside the first contact hole so that a recess is formed to be depressed from a top surface of the first interlayer insulating layer toward the substrate;   depositing the lower electrode material film on the first interlayer insulating layer so as to cover the first contact plug;   forming a lower electrode having a flat, continuous top surface by planarizing the deposited lower electrode material film by polishing a top surface of the lower electrode material film until a depression in the top surface of the lower electrode material film disappears so that only a single material is polished in the polishing and the lower electrode material film is left behind throughout a wafer, the depression created in the top surface into which a shape of the recess is transferred;   forming, on the lower electrode material film, variable resistance layer material films and an upper electrode material film in this order, the variable resistance layer material film being to become the variable resistance layer, and the upper electrode material film to become the upper electrode; and   forming the variable resistance element by patterning the lower electrode material film, the variable resistance layer material films, and the upper electrode material film.   
     
     
         6 . (canceled) 
     
     
         7 . The method of manufacturing a semiconductor memory device according to  claim 5 ,
 wherein the lower electrode is composed of a plurality of layers including a first lower electrode and a second lower electrode, and   said forming of a lower electrode material film which has a planarized top surface includes:   depositing a first lower electrode material film on the first interlayer insulating layer so as to cover the first contact plug, the first lower electrode material film being to become the first lower electrode;   planarizing, by polishing, a top surface of the deposited first lower electrode material film; and   depositing, on the planarized top surface of the first lower electrode material film, a second lower electrode material film which has a uniform thickness and is to become the second lower electrode.   
     
     
         8 . The method of manufacturing a semiconductor memory device according to  claim 5 ,
 wherein the lower electrode is composed of a plurality of layers including a first lower electrode and a second lower electrode, and   said forming of a lower electrode material film which has a planarized top surface includes:   depositing a first lower electrode material film on the first interlayer insulating layer so as to cover the first contact plug, the first lower electrode material film being to become the first lower electrode;   depositing a second lower electrode material film on the first lower electrode material film, the second lower electrode material film being to become the second lower electrode; and   planarizing, by polishing, a top surface of the second lower electrode material film.   
     
     
         9 . The method of manufacturing a semiconductor memory device according to  claim 5 ,
 wherein said planarizing of the top surface of any one of the lower electrode material film, the first lower electrode material film, and the second lower electrode material film is performed by chemical mechanical polishing.   
     
     
         10 . The method of manufacturing a semiconductor memory device according to  claim 5 ,
 wherein the lower electrode material film, the variable resistance layer material films, and the upper electrode material film are patterned by dry-etching in said forming of a variable resistance element.   
     
     
         11 . The semiconductor memory device according to  claim 1 ,
 wherein said second variable resistance layer is thinner than said first variable resistance layer.   
     
     
         12 . The method of manufacturing a semiconductor memory device according to  claim 5 ,
 wherein the variable resistance layer is brought into a state to be ready to start resistance change, by locally short-circuiting part of the second variable resistance layer.   
     
     
         13 . The method of manufacturing a semiconductor memory device according to  claim 5 ,
 wherein the second variable resistance layer has a thickness which is less than a crosswise width of the recess.