Inspection method for an active matrix substrate

Abstract

An active matrix substrate including a substrate, a plurality of scan lines, a plurality of data lines, a plurality of independent common line patterns, and a plurality of pixels is provided. The scan lines, data lines, and common line patterns are disposed on the substrate. The pixels are arranged in array on the substrate, wherein each pixel is electrically connected to corresponding scan line and data line, and the common line patterns are distributed under each pixel. Each pixel includes a plurality of active components and a plurality of pixel electrodes. Each of the pixel electrodes is electrically connected to corresponding scan line and data line through different active components. The capacitance coupling effect between each of the pixel electrodes and common line patterns are different. Additionally, an inspection method for the active matrix substrate and a liquid crystal display having the active matrix substrate are further provided.

1 . A method for inspecting the active matrix substrate, the active matrix substrate comprising: a substrate; a plurality of scan lines, a plurality of data lines, and a plurality of common line patterns disposed on the substrate; a plurality of pixels arranged in array on the substrate, each pixel being electrically connected to a corresponding scan line and a data line, and the common line patterns being distributed under each pixel, each pixel comprising a plurality of active components and a plurality of pixel electrodes, each of the pixel electrodes being electrically connected to a corresponding data line through different active components, and a capacitance coupling effect between one pixel electrode and one common line pattern being different from that between another pixel electrode and another common line pattern, the method comprising:
 providing different voltage levels or wave patterns to each common line pattern, so as to increase voltage difference between the pixel electrodes of each pixel; and   generating a short circuit determination according to the voltage difference.   
     
     
         2 . The inspection method as claimed in  claim 1 , wherein two of the common line patterns are respectively applied with a first voltage and a second voltage lower than the first voltage. 
     
     
         3 . The inspection method as claimed in  claim 2 , wherein the first voltage is a common voltage. 
     
     
         4 . The inspection method as claimed in  claim 2 , wherein the first voltage is higher than a common voltage. 
     
     
         5 . The inspection method as claimed in  claim 4 , wherein the common voltage is approximately between −50 V and 50 V. 
     
     
         6 . The inspection method as claimed in  claim 2 , wherein the voltage difference between the first voltage and the second voltage is approximately between 0 V and 100 V. 
     
     
         7 . The inspection method as claimed in  claim 2 , wherein the first voltage is lower than a common voltage. 
     
     
         8 . The inspection method as claimed in  claim 1 , wherein three of the common line patterns are respectively coupled to a first voltage, a second voltage lower than the first voltage, and a third voltage lower than the second voltage. 
     
     
         9 . The inspection method as claimed in  claim 8 , wherein the first voltage is a common voltage. 
     
     
         10 . The inspection method as claimed in  claim 9 , wherein the common voltage is approximately between −50 V and 50 V. 
     
     
         11 . The inspection method as claimed in  claim 8 , wherein the first voltage is lower than a common voltage. 
     
     
         12 . The inspection method as claimed in  claim 8 , wherein the first voltage is higher than a common voltage. 
     
     
         13 . The inspection method as claimed in  claim 8 , wherein the voltage difference between the first voltage and the second voltage is approximately between 0 V and 100 V. 
     
     
         14 . The inspection method as claimed in  claim 1 , further comprising charging the pixel electrodes, wherein the step of providing different voltage levels to each common line pattern is performed after the pixel electrodes are charged.