Delay adjustment device, semiconductor device and delay adjustment method

Abstract

A semiconductor device including an adjustment mode and a normal operation mode, including a first terminal to be coupled to the memory and configured to output a read command to the memory in the adjustment mode and not to output a write command in the adjustment mode, and a second terminal to be coupled to the memory and configured to receive a data strobe signal from the memory in the adjustment mode and not to output a signal to the memory in the adjustment mode.

1 . A semiconductor device including an adjustment mode and a normal operation mode, the semiconductor device comprising:
 a first terminal to be coupled to the memory and configured to output a read command to the memory in the adjustment mode and not to output a write command in the adjustment mode; and   a second terminal to be coupled to the memory and configured to receive a data strobe signal from the memory in the adjustment mode and not to output a signal to the memory in the adjustment mode.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the second terminal is configured to output another command to the memory in the normal operation mode. 
     
     
         3 . The semiconductor device according to  claim 1 , further comprising:
 a valid signal output circuit configured to output a valid signal; and   a strobe value retrieve unit coupled to the second terminal and the valid signal output circuit to store the data strobe signal based on the valid signal.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein the valid signal output circuit is configured to output another valid signal later than the valid signal, and the strobe value retrieve unit is configured to store the data strobe signal based on the another valid signal. 
     
     
         5 . The semiconductor device according to  claim 3 , further comprising:
 a third terminal to be coupled to the memory and configured to receive a data signal;   a mask circuit coupled to the second terminal and the strobe value retrieve unit;   a delay unit coupled to the mask circuit;   a flip-flop coupled to the third terminal and the delay unit; and   a variable delay circuit coupled to the flip-flop.   
     
     
         6 . The semiconductor device according to  claim 5 , further comprising an adjustment circuit coupled to the strobe value retrieve unit and the valid signal output unit and configured to output the read command in the adjustment mode. 
     
     
         7 . The semiconductor device according to  claim 6 , wherein the second terminal is configured to output another command to the memory in the normal operation mode, and the semiconductor device further comprises a switch coupled to the adjustment circuit to output one of the read command and the another command. 
     
     
         8 . The semiconductor device according to  claim 7 , further comprising a processing circuit coupled to the variable delay circuit and the adjustment circuit, the processing circuit being configured to output the other command. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein the memory comprises an SDRAM (Synchronous Dynamic Random Access Memory). 
     
     
         10 . The semiconductor device according to  claim 8 , wherein the memory comprises a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).