Strained-induced mobility enhancement nano-device structure and integrated process architecture for cmos technologies

Abstract

A CMOS semiconductor integrated circuit device includes an NMOS device comprising a gate region, a source region, and a drain region and an NMOS channel region formed between the source region and drain region. A silicon carbide material is formed within the source region and formed within the drain region. The silicon carbide material causes the channel region to be in a tensile mode. The CMOS device also has a PMOS device comprising a gate region, a source region, and a drain region. The PMOS device has a PMOS channel region formed between the source region and the drain region. A silicon germanium material is formed within the source region and formed with in the drain region. The silicon germanium material causes the channel region to be in a compressive mode.

1 . A method for forming a CMOS integrated circuit device, the method comprising:
 providing a semiconductor substrate;   forming a gate layer overlying the semiconductor substrate;   patterning the gate layer to form an NMOS gate structure including edges and a PMOS gate structure including edges;   forming a dielectric layer overlying the NMOS gate structure to protect the NMOS gate structure including the edges and overlying the PMOS gate structure to protect the PMOS gate structure including the edges;   simultaneously etching a first source region and a first drain region adjacent to the NMOS gate structure and second source region and second drain region adjacent to the PMOS gate structure using the dielectric layer as a protective layer;   depositing silicon carbide material into the first source region and the first drain region to cause a channel region between the first source region and the first drain region of the NMOS gate structure to be strained in a tensile mode;   depositing silicon germanium material into the second source region and second drain region to cause the channel region between the second source region and the second drain region of the PMOS gate structure to be strained in a compressive mode.   
     
     
         2 . The method of  claim 1  wherein the tensile mode increases an electron mobility. 
     
     
         3 . The method of  claim 1  wherein the compressive mode increases a hole mobility. 
     
     
         4 . The method of  claim 1  wherein the channel region of the PMOS device has a length of 90 nanometers and less. 
     
     
         5 . The method of  claim 1  wherein the channel region of the NMOS device has a length of 90 nanometers and less. 
     
     
         6 . The method of  claim 1  wherein the silicon germanium material is an epitaxial material. 
     
     
         7 . The method of  claim 1  wherein the silicon carbide material is an epitaxial material. 
     
     
         8 . The method of  claim 1  wherein the silicon germanium material has a thickness ranging from about 200 Angstroms to 1000 Angstroms. 
     
     
         9 . The method of  claim 1  wherein the silicon carbide material has a thickness ranging from about 200 Angstroms to 1000 Angstroms. 
     
     
         10 . The method of  claim 1  further comprising forming sidewall spacers on the edges of the NMOS gate structure and the edges of the PMOS gate structure. 
     
     
         11 . The method of  claim 1  wherein the depositing the silicon germanium material is an in-situ doped process using a boron species, the boron species having a concentration ranging from about 10 19  to 10 20  atoms/cm 3 . 
     
     
         12 . The method of  claim 1  wherein the depositing the silicon carbide material is an in-situ doped process using a phosphorus species, the phosphorus species having a concentration ranging from about 10 19  to 10 20  atoms/cm 3 . 
     
     
         13 . The method of  claim 1  further comprising forming a refractory metal layer overlying the first source region and first drain region and the second source region and the second drain region. 
     
     
         14 . The method of  claim 1  wherein the first source region is an elevated first source region and the first drain region is an elevated first drain region; the second source region is an elevated second source region and the second drain region is an elevated second drain region.