US2012169372A1PendingUtilityA1

Differential logic circuit, frequency divider, and frequency synthesizer

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Assignee: WANG JIANQINPriority: Jan 27, 2010Filed: Mar 15, 2012Published: Jul 5, 2012
Est. expiryJan 27, 2030(~3.6 yrs left)· nominal 20-yr term from priority
Inventors:Jianqin Wang
H03K 23/662H03K 19/01855
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Claims

Abstract

A differential logic circuit including a current source circuit which is connected to a current control terminal and generates a current, the current value is controlled by a signal received from the current control terminal, a differential unit which, based on the current from the current source circuit, inputs a plurality of logic signals, performs a logic operation, and outputs a result of the logic operation from a pair of differential signal output terminals thereof, a load circuit which is connected to the pair of differential signal output terminals, and a load control circuit which monitors a change of the current value and controls a load of the load circuit based on a result of the monitoring.

Claims

exact text as granted — not AI-modified
1 . A differential logic circuit comprising:
 a current source circuit which is connected to a current control terminal and generates a current, the current value is controlled by a signal received from the current control terminal;   a differential logic unit which, based on the current from the current source circuit, inputs a plurality of logic signals, performs a logic operation, and outputs a result of the logic operation from a pair of differential signal output terminals thereof;   a load circuit which is connected to the pair of differential signal output terminals; and   a load control circuit which monitors a change of the current value and controls a load of the load circuit based on a result of the monitoring.   
     
     
         2 . The differential logic circuit according to  claim 1 , wherein the load control circuit controls the load of the load circuit such that a direct-current output voltage of the pair of differential signal output terminals is constant.

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