Data driver and display apparatus using the same including clock control circuit and shift register circuit

Abstract

A circuit includes a first shift register configured to be reset with a reset signal, to shift a first pulse signal and output the shifted first pulse signal as a second pulse signal, and a second shift register configured to be reset with the first pulse signal, to shift the second pulse signal and to output the shifted second pulse signal as a third pulse signal.

1 . A circuit comprising:
 a first shift register configured to be reset with a reset signal, to shift a first pulse signal and output the shifted first pulse signal as a second pulse signal; and   a second shift register configured to be reset with the first pulse signal, to shift the second pulse signal and to output the shifted second pulse signal as a third pulse signal.   
     
     
         2 . The circuit according to  claim 1 , further comprising a third shift register configured to be reset with the second pulse signal, to shift the third pulse signal and to output the shifted third pulse signal. 
     
     
         3 . A circuit comprising:
 a first shift register including a first reset node, a first input node coupled to a first node and a first output node coupled to a second node; and   a second shift register including a second reset node coupled to the first node, a second input node coupled to the second node, and a second output node coupled to a third node.   
     
     
         4 . The circuit according to  claim 3 , further comprising a third shift register including a third reset node coupled to the second node, a third input node coupled to the third node, and a third output node. 
     
     
         5 . The circuit according to  claim 4 , further comprising a clock control circuit including a first clock node coupled to the first shift register, a second clock node coupled to the second shift register and a third clock node coupled to the third shift register. 
     
     
         6 . The circuit according to  claim 5 ,
 wherein the first shift register is configured to be reset with a reset signal inputted to the reset node and to shift a first pulse signal inputted to the first node and output the shifted first pulse signal to the second node as a second pulse signal,   wherein the second shift register is configured to be reset with the first pulse signal and to shift the second pulse signal and output the shifted second pulse signal to third node as a third pulse signal, and   wherein the third shift register is configured to be reset with the second pulse signal and to shift the third pulse signal and output the shifted third pulse signal as a fourth pulse signal.   
     
     
         7 . The circuit according to  claim 6 , wherein the clock control circuit is configured to start supplying a first clock signal through the first clock node in response to the reset signal and to stop supplying the first clock signal in response to the third pulse signal. 
     
     
         8 . The circuit according to  claim 7 , wherein the clock control circuit is further configured to start supplying a second clock signal through the second clock node in response to the first pulse signal and to stop supplying the second clock signal in response to the fourth pulse signal. 
     
     
         9 . A semiconductor device, comprising:
 a first shift register including a first reset node, a first input node coupled to a first node and a first output node coupled to a second node; and   a second shift register including a second reset node coupled to the first node, a second input node coupled to the second node and a second output node coupled to a third node.   
     
     
         10 . The semiconductor device according to  claim 9 , further comprising a third shift register including a third reset node coupled to the second node, a third input node coupled to the third node and a third output node. 
     
     
         11 . The semiconductor device according to  claim 10 , further comprising a clock control circuit including a first clock node coupled to the first shift register, a second clock node coupled to the second shift register and a third clock node coupled to the third shift register.