Method and system for performing dma in a multi-core system-on-chip using deadline-based scheduling

Abstract

A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.

1 . A direct memory access (DMA) engine processing transfer requests of a data processing system, comprising:
 a command processor configured to receive and interpret transfer requests of the data processing system;   a transfer memory connected to the command processor and having, for each of the transfer requests, data fields including transfer priority and transfer deadline;   a transaction dispatcher connected to the transfer memory and configured to handle command and data transfers to and from a DRAM controller and a global bus interface in accord with transfer requests interpreted by the command processor;   a channel scanner connected to the transfer memory and configured to determine a transfer urgency, and to schedule among multiple transfer requests interpreted by the command processor based on the determined transfer urgency of the respective transfer requests so as to control the transaction dispatcher, wherein the transfer urgency is based on both the transfer deadline and the transfer priority, such that higher priority transfers have higher urgency, and equal priority transfers with earlier deadlines have higher urgency, and wherein the transfer priority is based on a hardness representing a penalty for missing a deadline and is also assigned to zero-deadline transfer requests wherein there is a penalty no matter how early the transfer completes.