US2012173864A1PendingUtilityA1
Flexible multi-processing system
Est. expiryJun 28, 2022(expired)· nominal 20-yr term from priority
G06F 9/30036G06F 9/3887G06F 9/3897G06F 15/8076H04M 2201/34G06F 9/3877
48
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Claims
Abstract
A processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, the engines adapted to minimize data exchange penalties by processing small in-out bit slices.
Claims
exact text as granted — not AI-modified1 - 20 . (canceled)
21 . An apparatus, comprising:
a computation unit configured to execute control software to process data for wireless transmission, wherein the control software includes a plurality of function calls respectively corresponding to a plurality of digital signal processing functions; a plurality of dedicated hardware engines configured to perform respective ones of the plurality of digital signal processing functions; and a switch fabric coupled to the computation unit and to the plurality of dedicated hardware engines, the switch fabric being configured to perform operations including reconfiguring the apparatus from processing data for transmission via a first wireless protocol to processing data for transmission via a second wireless protocol.
22 . The apparatus of claim 21 , wherein the computation unit is configured to cause at least first and second dedicated hardware engines of the plurality of dedicated hardware engines to:
responsive to ones of the plurality of function calls included in the control software, perform the corresponding digital signal processing functions; and subsequently send information to the computation unit.
23 . The apparatus of claim 21 , wherein the computation unit comprises:
a scalar computation unit configured to provide configuration settings to the plurality of dedicated hardware engines at a beginning of a computation sequence; and a vector co-processor configured to perform parallel computational operations.
24 . The apparatus of claim 23 , wherein the scalar computation unit is further configured to cause the vector co-processor to perform the parallel computational operations in response identifying the parallel computational operations in the control software.
25 . The apparatus of claim 21 , wherein the first wireless protocol is a cellular radio protocol, and wherein the second wireless protocol is a short-range wireless protocol.
26 . The apparatus of claim 21 , wherein the plurality of dedicated hardware engines are implemented as part of an integrated circuit.
27 . The apparatus of claim 21 , wherein one or more of the plurality of dedicated hardware engines is configured to be reconfigured from use with the first wireless protocol to use with the second wireless protocol by changing configuration settings.
28 . The apparatus of claim 21 , wherein the plurality of dedicated hardware engines includes at least two different dedicated hardware engines selected from the group consisting of:
a convolutional decoding engine, a modulation engine, a transform engine, an error correction engine, and a cryptographic engine.
29 . A wireless device, comprising:
a radio frequency (RF) front end configured to receive an RF signal from an antenna; and a logic portion coupled to the RF front-end, the logic portion including:
a computation unit configured to execute control software to process data packets for transmission via a wireless protocol, wherein the control software includes a plurality of function calls respectively corresponding to a plurality of digital signal processing functions;
a plurality of dedicated hardware engines configured to perform respective ones of the plurality of digital signal processing functions; and
a switch fabric coupled to the computation unit and to the plurality of dedicated hardware engines, the switch fabric being configured to perform operations including reconfiguring the logic portion from processing data for transmission via a first wireless protocol to processing data for transmission via a second wireless protocol.
30 . The wireless device of claim 29 , wherein the reconfiguring the logic portion includes disabling one or more of the plurality of dedicated hardware engines without disabling other ones of the plurality of dedicated hardware engines.
31 . The wireless device of claim 29 , wherein the plurality of dedicated hardware engines includes a modulation engine and a cryptographic engine.
32 . The wireless device of claim 29 , further comprising:
a cellular radio core configured to support transmission via the first wireless protocol; and a short-range wireless transceiver core configured to support transmission via the second wireless protocol.
33 . The wireless device of claim 29 , wherein the plurality of dedicated hardware engines includes an orthogonal frequency division multiplexing (OFDM) engine.
34 . The wireless device of claim 29 , wherein the first dedicated hardware engines includes a transform engine and an error correction engine.
35 . The wireless device of claim 34 , wherein the transform engine is an FHT engine and the error correction engine is a CRC engine.
36 . The wireless device of claim 29 , wherein the computation unit is configured to provide configuration and parametric settings to the plurality of dedicated hardware engines at a beginning of a computation sequence.
37 . The wireless device of claim 29 , wherein the plurality of dedicated hardware engines are implemented in one application-specific integrated circuit.
38 . The wireless device of claim 29 , wherein the wireless device is configured to communicate one or more of the data packets in parallel via at least two different wireless protocols.
39 . An apparatus, comprising:
first means for executing control software to process data packets for transmission via a wireless protocol, wherein the control software includes a plurality of function calls respectively corresponding to a plurality of digital signal processing functions a plurality of dedicated hardware engines configured to perform respective ones of the plurality of digital signal processing functions; and second means for reconfiguring the apparatus from processing data for transmission via a first wireless protocol to processing data for transmission via a second wireless protocol, the reconfiguring including disabling one or more of the plurality of dedicated hardware engines without disabling remaining ones of the plurality of dedicated hardware engines.
40 . The apparatus of claim 39 , wherein the plurality of dedicated hardware engines are implemented as part of a single integrated circuit.Cited by (0)
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