Delay locked loop circuit for preventing failure of coarse locking

Abstract

A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. Accordingly, a failure of a coarse locking may be prevented thus facilitating improved circuit performance.

1 . A delay locked loop circuit comprising:
 a delay locked loop configured to receive an external signal and perform a delay lock process;   a frequency detector configured to delay an input frequency signal which is obtained by delaying the external signal to generate a plurality of strobe signals, and output a check signal indicating whether the frequency of the input frequency signal is equal to or lower than a reference frequency if all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal; and   a direct phase detector configured to receive the check signal from the frequency detector, control a coarse locking window of the delay locked loop circuit on the basis of the check signal, and generate a pair of phase detection signals indicating logic level of the external clock.