Symmetric Phase Detector

Abstract

In one embodiment, a circuit includes a first mixer cell and a second mixer cell that each have respectively a first cell input, a second cell input, and a cell output. The circuit includes a first circuit input configured to receive a first input signal having a first phase. The first circuit input is connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell. The circuit includes a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value. The second circuit input is connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell.

1 . A circuit comprising:
 a first mixer cell and a second mixer cell, each having respectively a first cell input, a second cell input, and a cell output;   a first circuit input configured to receive a first input signal having a first phase, the first circuit input being connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell;   a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value, the second circuit input being connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell; and   a circuit output configured to receive a combined output from respective cell outputs of the first mixer cell and the second mixer cell and output the combined output, the combined output having a current that is proportional to an error offset from the nominal value.   
     
     
         2 . The circuit of  claim 1 , wherein the nominal value is 90 degrees. 
     
     
         3 . The circuit of  claim 1 , wherein each of the first mixer cell and the second mixer cell comprises a multiplying mixer cell. 
     
     
         4 . The circuit of  claim 3 , wherein the multiplying mixer cell comprises a Gilbert cell. 
     
     
         5 . The circuit of  claim 1 , wherein the circuit is a phase detector. 
     
     
         6 . The circuit of  claim 1 , further comprising a current mirror configured to mirror respective currents from cell outputs of the first mixer cell and the second mixer cell, wherein the combined output being a sum of the respective mirrored currents. 
     
     
         7 . The circuit of  claim 1 , further comprising one or more current sources configured to adjust the combined output. 
     
     
         8 . A method comprising:
 receiving at a first circuit input a first input signal having a first phase, the first circuit input being connect to a first cell input of a first mixer cell and a second cell input of a second mixer cell, the first mixer cell and the second mixer cell each having respectively a first cell input, a second cell input and a cell output;   receiving at a second circuit input a second input signal having a second phase separated from the first phase by a nominal value, the second circuit input being connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell; and   receiving at a circuit output a combined output from respective cell outputs of the first mixer cell and the second mixer cell and output the combined output, the combined output having a current that is proportional to an error offset from the nominal value.   
     
     
         9 . The method of  claim 8 , wherein the nominal value is 90 degrees. 
     
     
         10 . The method of  claim 8 , wherein each of the first mixer cell and the second mixer cell comprises a multiplying mixer cell. 
     
     
         11 . The method of  claim 10 , wherein the multiplying mixer cell comprises a Gilbert cell. 
     
     
         12 . The method of  claim 8 , further comprising mirroring by a current mirror respective currents from cell outputs of the first mixer cell and the second mixer cell, wherein the combined output being a sum of the respective mirrored currents. 
     
     
         13 . The method of  claim 8 , further comprising adjusting by one or more current sources the combined output.