Method for fabricating trench dmos transistor

Abstract

A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and forming a metal silicide layer on the diffusion layer and the trench gate. Effective result of the present invention is achieved with lower cost and improved efficiency of fabrication.

1 . A method for fabricating trench DMOS transistor, comprising:
 forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate;   etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to define a trench;   forming a gate oxide layer on the inner wall of the trench;   filling up the trench with polysilicon so as to form a trench gate;   removing the barrier layer and the oxide layer;   implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer;   coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon;   implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain;   forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and   forming a metal silicide layer on the diffusion layer and the trench gate.   
     
     
         2 . The method for fabricating trench DMOS transistor according to  claim 1 , wherein the semiconductor substrate comprises an N-type silicon substrate and an N-type epitaxial layer arranged thereon, and wherein in forming the trench gate, first form a polysilicon layer on the barrier layer, and etch back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer. 
     
     
         3 . The method for fabricating trench DMOS transistor according to  claim 2 , wherein the trench is located in the N-type epitaxial layer. 
     
     
         4 . The method for fabricating trench DMOS transistor according to  claim 1 , wherein the oxide layer is formed by means of thermal oxidation or chemical vapor deposition or physical vapor deposition. 
     
     
         5 . The method for fabricating trench DMOS transistor according to  claim 4 , wherein the oxide layer is of silicon dioxide with a thickness of 250 Å to 350 Å. 
     
     
         6 . The method for fabricating trench DMOS transistor according to  claim 1 , wherein the barrier layer is formed by means of chemical vapor deposition or physical vapor deposition. 
     
     
         7 . The method for fabricating trench DMOS transistor according to  claim 6 , wherein the barrier layer is of silicon nitride with a thickness of 2500 Å to 3500 Å. 
     
     
         8 . The method for fabricating trench DMOS transistor according to  claim 1 , wherein the gate oxide layer is formed by means of thermal oxidation or rapid annealing oxidation. 
     
     
         9 . The method for fabricating trench DMOS transistor according to  claim 8 , wherein the gate oxide layer is of silicon dioxide or nitrogen-containing silicon dioxide with a thickness of 300 Å to 1000 Å. 
     
     
         10 . The method for fabricating trench DMOS transistor according to  claim 1 , wherein during the formation of the diffusion layer, P-type ions are implanted into the semiconductor substrate. 
     
     
         11 . The method for fabricating trench DMOS transistor according to  claim 10 , wherein the P-type ions are boron ions implanted at a dosage of 1E13/cm 2  to 3E13/cm 2  with energy of 70KeV to 100KeV. 
     
     
         12 . The method for fabricating trench DMOS transistor according to  claim 1 , wherein during the formation of the source/drain, N-type ions are implanted into the diffusion layer. 
     
     
         13 . The method for fabricating trench DMOS transistor according to  claim 12 , wherein the N-type ions are arsenic ions implanted at a dosage of 1E16/cm 2  to 5E16/cm 2  with energy of 70KeV to 130KeV.