Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits

Abstract

Circuits for measuring and characterizing random variations in device characteristics of integrated circuit devices.

1 . A testing apparatus for characterizing device mismatch in a semiconductor integrated circuit, comprising:
 a plurality of test circuits, wherein each test circuit is configured for obtaining subthreshold DC voltage characteristic data for a device pair of an integrated circuit; and   a multiplexer, for selectively outputting an output voltage from each test circuits.   
     
     
         2 . The testing apparatus of  claim 1 , wherein a portion of the plurality of test circuits are configured for testing the same device pair. 
     
     
         3 . The testing apparatus of  claim 1 , wherein the plurality of test circuits are divided into groups of test circuits, wherein each group of the test circuits comprises the same test circuits. 
     
     
         4 . The testing apparatus of  claim 1 , wherein each group of test circuits is associated with a multiplexer, wherein the multiplexers are controlled such that the output voltages from similar test circuits in each group are simultaneously measured. 
     
     
         5 . The testing apparatus of  claim 1 , further comprising a database for storing the subthreshold DC voltage characteristic data. 
     
     
         6 . The testing apparatus of  claim 5 , further comprising a processing unit for statistically processing the subthreshold DC voltage characteristic data stored in database for determining a distribution of device mismatch of the integrated circuit. 
     
     
         7 . A testing apparatus for characterizing device mismatch in a semiconductor integrated circuit, comprising:
 a plurality of test circuits, wherein each test circuit is configured for obtaining subthreshold DC voltage characteristic data for a device pair of an integrated circuit, the device pair selected by a test circuit of the plurality of test circuits corresponding to the device pair, wherein the device pair comprise neighboring first and second transistors, wherein the subthreshold DC voltage characteristic data for the selected device pair comprises an output DC voltage V ouT  as a function of an input DC voltage V IN , wherein V IN  is applied to a gate of at least one of the first and second transistors and wherein V ouT  is obtained at a common node connection of the first and second transistors, and wherein the DC voltage characteristic data is obtained with the first and second transistor devices operating in a subthreshold region; and   a multiplexer, for selectively outputting an output voltage from each test circuits.   
     
     
         8 . The testing apparatus of  claim 7 , wherein at least two of the plurality of test circuits are configured for testing the device pair. 
     
     
         9 . The testing apparatus of  claim 7 , wherein the plurality of test circuits are divided into groups of test circuits, wherein each group of the test circuits comprises a same type of test circuit. 
     
     
         10 . The testing apparatus of  claim 9 , wherein each group of test circuits is associated with a different multiplexer, wherein the multiplexers are controlled such that the output voltages from the same type test circuits in each group are simultaneously measured. 
     
     
         11 . The testing apparatus of  claim 9 , further comprising a database for storing the subthreshold DC voltage characteristic data. 
     
     
         12 . The testing apparatus of  claim 12 , further comprising a processing unit for statistically processing the subthreshold DC voltage characteristic data stored in database for determining a distribution of device mismatch of the integrated circuit. 
     
     
         13 . A test circuit comprising:
 a pair of access transistors;   a bitline pair comprising a first bitline and a second bitline connected to respective transistors of the pair of access transistors, respectively;   a pair of storage nodes connected to respective transistors of the pair of access transistors;   a wordline commonly connected to gate terminals of the pair of access transistors; and   a pair of pull-down transistors coupled with a pair of pull-up transistors, wherein each storage node of the pair of storage nodes is disposed between a respective pull-down transistor and a respective pull-up transistor.   
     
     
         14 . The test circuit of  claim 13 , wherein gates of the pair of pull-down transistors are connected to a ground voltage. 
     
     
         15 . The test circuit of  claim 13 , wherein gates of the pair of access transistors are connected to a ground voltage. 
     
     
         16 . The test circuit of  claim 13 , wherein gates of the pair of access transistors are connected to a constant voltage. 
     
     
         17 . The test circuit of  claim 13 , wherein a first storage node of the pair of storage nodes is connected to a gate terminal of a first pull-down transistor of the pair of pull-down transistors and connected to a drain terminal of a second pull-down transistor of the pair of pull-down transistors, and a second storage node of the pair of storage nodes is connected to a gate terminal of a second pull-down transistor of the pair of pull-down transistors and connected to a drain terminal of a first pull-down transistor of the pair of pull-down transistors. 
     
     
         18 . The test circuit of  claim 13 , wherein a first storage node of the pair of storage nodes is connected to a gate terminal of a first pull-up transistor of the pair of pull-down transistors and connected to a source terminal of a second pull-up transistor of the pair of pull-up transistors, and a second storage node of the pair of storage nodes is connected to a gate terminal of a second pull-up transistor of the pair of pull-down transistors and connected to a drain terminal of a first pull-up transistor of the pair of pull-up transistors.