System For Accessing Non-Volatile Memory

Abstract

Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.

1 . A system including non-Flash re-writeable non-volatile memory, comprising:
 a semiconductor substrate including circuitry fabricated on the semiconductor substrate, the circuitry including a processor and a memory controller in electrical communication with each other;   a memory plane in direct contact with and fabricated directly above the semiconductor substrate;   a two-terminal cross-point memory array embedded in the memory plane and including a plurality of first conductive array lines orthogonally oriented to a plurality of second conductive array lines to form a plurality of cross-points, the plurality of first and second conductive array lines are in electrical communication with the memory controller; and   a plurality of re-writeable non-volatile memory elements (ME's), each ME having exactly two terminals, each ME is positioned between one of the cross-points and has one of its two terminals directly electrically coupled with the first conductive array line at its respective cross-point and the other of its two terminals directly electrically coupled with the second conductive array line at its respective cross-point, and each ME is directly electrically in series with the first and second conductive array lines at its respective cross-point,   wherein the memory controller is specifically configured to perform data operations on the two-terminal cross-point memory array without having to perform an erase operation prior to a write operation and to perform random access data operations on the two-terminal cross-point memory array at a data granularity ranging from a single bit of data in a single ME to at least one block of data in a subset of the plurality of ME's, and   the memory controller is configured to perform at least some data operations on the two-terminal cross-point memory array using a file structure including a header section, a data section, and a footer section that includes error correcting code (ECC), and   the header section, the footer section or both are stored in one or more portions of the two-terminal cross-point memory array other than a portion for the data section.   
     
     
         2 . The system of  claim 1 , wherein each ME is configured to store exactly one bit of data. 
     
     
         3 . The system of  claim 1 , wherein each ME is configured to store at least two bits of data. 
     
     
         4 . The system of  claim 1 , wherein the file structure is configured for use with a File Allocation Table (FAT) file system. 
     
     
         5 . The system of  claim 1 , wherein the file structure comprises a memory block. 
     
     
         6 . The system of  claim 5 , wherein the memory block comprises an identifier associated with the two-terminal cross-point memory array and the identifier is selected from the group consisting of a row of memory, a portion of a row of memory, a memory column, a memory bank, a memory plane, and a sub-plane of a memory plane. 
     
     
         7 . The system of  claim 1 , wherein the footer section further includes information associated with defective bit replacement, defective column replacement, or both. 
     
     
         8 . The system of  claim 1 , wherein the data and footer sections are associated with the header section. 
     
     
         9 . The system of  claim 8 , wherein the header section includes information associated with its respective data section. 
     
     
         10 . The system of  claim 1 , wherein the memory controller is configured to map a physical address space of the two-terminal cross-point memory array to a logical address space. 
     
     
         11 . The system of  claim 1  and further comprising: at least one bus included in the circuitry and electrically coupled with the processor and the memory controller. 
     
     
         12 . The system of  claim 11 , wherein the two-terminal cross-point memory array is electrically coupled with the at least one bus. 
     
     
         13 . The system of  claim 1  and further comprising:
 a plurality of the memory planes that are vertically stacked upon one another and are in contact with one another, and a bottommost of the plurality of the memory planes is in direct contact with the semiconductor substrate. 
 
     
     
         14 . The system of  claim 13 , wherein the one or more portions are disposed in a different memory plane than a memory plane of the portion for the data section. 
     
     
         15 . The system of  claim 13 , wherein at least one of the plurality of the memory planes is divided into memory sub-planes. 
     
     
         16 . The system of  claim 15 , wherein the one or more portions are disposed in a different memory sub-plane than a memory plane or memory sub-plane of the portion for the data section. 
     
     
         17 . The system of  claim 1 , wherein each ME comprises an ion reservoir including mobile ions and a tunnel barrier that are electrically in series with each other and with the two terminals of the ME. 
     
     
         18 . The system of  claim 17 , wherein and each ME is operative to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals of the ME, and wherein data stored in the ME is retained in an absence of electrical power. 
     
     
         19 . The system of  claim 17 , wherein the mobile ions are oxygen ions. 
     
     
         20 . The system of  claim 19 , wherein the tunnel barrier is permeable to oxygen ions when a write voltage is applied across the two terminals of the ME.