Semiconductor device

Abstract

A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12 . The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4 . The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10 . The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.

1 . A semiconductor device including a MISFET; said semiconductor device comprising:
 a first film that covers at least a portion of an upper part of a source/drain of said MISFET; said first film being of a film thickness thinner than the height of a gate electrode; and   a second film arranged on said first film; wherein   said first film and said second film are films subjected to compressive stress;   a compressive stress of said first film is lower than that of said second film; and   gate sidewall spacers arranged on both sides of said gate electrode; said gate sidewall spacers being of a cross-sectional shape of an uppercase letter L.   
     
     
         2 . The semiconductor device according to  claim 1  wherein said second film is a silicon nitride film. 
     
     
         3 . The semiconductor device according to  claim 2  wherein said second film contains hydrogen. 
     
     
         4 . The semiconductor device according to  claim 1  wherein said first film is a silicon nitride film. 
     
     
         5 . The semiconductor device according to  claim 4  wherein said first film contains hydrogen. 
     
     
         6 . The semiconductor device according to  claim 1  wherein said first film is a silicon oxide film. 
     
     
         7 . The semiconductor device according to  claim 1  wherein said first film has a thickness not less than 5 nm. 
     
     
         8 . The semiconductor device according to  claim 7  wherein said first film has a thickness not less than 10 nm. 
     
     
         9 . The semiconductor device according to  claim 1  wherein said MISFET is a p-channel MISFET. 
     
     
         10 . The semiconductor device according to  claim 1  further comprising:
 a metal silicide film at an interface between said first film and said source/drain. 
 
     
     
         11 . The semiconductor device according to  claim 1  wherein said first and second films are removed at least in an area above said gate electrode. 
     
     
         12 . The semiconductor device according to  claim 1  further comprising:
 a gate sidewall spacers arranged on both sides of said gate electrode; said gate sidewall spacers being lower in height than said gate electrode. 
 
     
     
         13 . The semiconductor device according to  claim 1  wherein
 said source/drain is sunk to a level lower than the gate insulating film lying below said gate electrode. 
 
     
     
         14 . The semiconductor device according to  claim 1  further comprising:
 a device isolation region formed around said source/drain; said device isolation region being sunk to a level lower than an upper surface of said source/drain; and 
 a diffusion layer sidewall spacers formed on a lateral side of said source/drain. 
 
     
     
         15 . A semiconductor device including a MISFET; said semiconductor device comprising:
 a first film that covers at least a portion of an upper part of a source/drain of said MISFET; said first film being of a film thickness thinner than a height of a gate electrode; and   a second film arranged on said first film; wherein   said first film is free of stress;   said second film is a film subjected to compressive stress; and   gate sidewall spacers arranged on both sides of said gate electrode; said gate sidewall spacers being of a cross-sectional shape of an uppercase letter L.   
     
     
         16 . A semiconductor device including a MISFET; said semiconductor device comprising:
 a first film that covers at least a portion of an upper part of a source/drain of said MISFET; said first film being of a film thickness thinner than a height of a gate electrode; and   a second film arranged on said first film; wherein   said first film and said second film are silicon nitride films;   said first film has a nitrogen concentration higher than that of said second film; and   gate sidewall spacers arranged on both sides of said gate electrode; said gate sidewall spacers being of a cross-sectional shape of an uppercase letter L.   
     
     
         17 . The semiconductor device according to  claim 16  wherein said first film contains hydrogen. 
     
     
         18 . The semiconductor device according to  claim 16  wherein said second film contains hydrogen.