Semiconductor memory device capable of preventing a shift of threshold voltage

Abstract

A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels.

1 . A semiconductor memory device comprising:
 a memory cell array connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number of 4 or more) in one memory cell are arrayed in a matrix; and   a control circuit configured to control a potential of the word line and the bit line in accordance with input data, and writing data in the memory cell,   wherein the control circuit performs a operation which applies a write voltage corresponding to data written to the memory cell, for every write data, and wherein the control circuit executes a verify operation for each write data after a write voltage application operation ends with respect to all n levels or to data of a predetermined unit.