Scalar integer instructions capable of execution with three registers

Abstract

A processing core implemented on a semiconductor chip is described. The processing core includes logic circuitry to identify whether vector instructions and integer scalar instructions are to be executed with two registers or three registers, where, in the case of two registers input operand information is destroyed in one of two registers, and, in the case of three registers input operand is not destroyed. The processing core also includes steering circuitry coupled to the logic circuitry. The steering circuitry is to control first data paths between scalar integer execution units and a scalar integer register bank such that two registers are accessed from the scalar register bank if two register execution is identified for the scalar integer instructions or three registers are accessed from the scalar integer register bank if three register execution is identified for the scalar integer instructions. The steering circuitry is also to control second data paths between vector execution units and a vector register bank such that two registers are accessed from the vector register bank if two register execution is identified for the vector instructions or three registers are accessed from the vector register bank if three register execution is identified for the vector instructions.

1 . A processing core implemented on a semiconductor chip, said processing core comprising:
 a) logic circuitry to identify whether vector instructions and integer scalar instructions are to be executed with two registers or three registers;   b) steering circuitry coupled to said logic circuitry, said steering circuitry to control:
 i) first data paths between scalar integer execution units and a scalar integer register bank such that two registers are accessed from said scalar register bank if two register execution is identified for said scalar integer instructions or three registers are accessed from said scalar integer register bank if three register execution is identified for said scalar integer instructions; 
 ii) second data paths between vector execution units and a vector register bank such that two registers are accessed from said vector register bank if two register execution is identified for said vector instructions or three registers are accessed from said vector register bank if three register execution is identified for said vector instructions. 
   
     
     
         2 . The processing core of  claim 1  wherein said integer scalar instructions include any of:
 logical AND NOT; 
 bit field extract; 
 zero high bits starting with specified bit position; 
 parallel bits deposit; 
 parallel bits extract; 
 shift 
 
     
     
         3 . The processing core of  claim 1  wherein said processing core is one of a plurality of processing cores implemented on said semiconductor chip. 
     
     
         4 . The processing core of  claim 1  where, in the case of three register execution, a third register is identified in prefix information of its respective instruction. 
     
     
         5 . The processing core of  claim 1  where said logic circuitry is located within a decode stage of said processing core. 
     
     
         6 . The processing core of  claim 5  wherein said processing core is a CISC processing core. 
     
     
         7 . A method, comprising:
 analyzing a vector instruction to determine if said vector instruction is to be executed with two registers or three registers;   if said vector instruction is to be executed with two registers, accessing two registers in a vector register bank as part of said vector instruction's execution;   if said vector instruction is to be executed with three registers, accessing three registers in said vector register bank as part of said vector instruction's execution;   analyzing a scalar integer instruction to determine if said scalar integer instruction is to be executed with two registers or three registers;   if said scalar integer instruction is to be executed with two registers, accessing two registers in a scalar integer register bank as part of said scalar integer instruction's execution; and,   if said scalar integer instruction is to be executed with three registers, accessing three registers in said scalar integer register bank as part of said scalar integer instruction's execution.   
     
     
         8 . The method of  claim 7  wherein said scalar integer instruction is any of the following scalar integer instructions:
 logical AND NOT; 
 bit field extract; 
 zero high bits starting with specified bit position; 
 parallel bits deposit; 
 parallel bits extract; 
 shift 
 
     
     
         9 . The method of  claim 7  wherein said analyzing of said vector instruction further includes analyzing prefix information of said vector instruction, and, said analyzing of said scalar integer instruction further includes analyzing prefix information of said scalar integer instruction. 
     
     
         10 . The method of  claim 9  wherein said analyzing of said vector instruction and said analyzing of said scalar integer instruction are performed in a decode logic stage of said processing core. 
     
     
         11 . The method of  claim 7  wherein an object code representation of said method is constructed with the following process:
 determining if input operand information of said scalar integer instruction is utilized after execution of said scalar integer instruction; 
 if input operand information of said scalar integer instruction is not utilized after execution of said scalar integer instruction, formatting said scalar integer instruction to specify execution of said scalar integer instruction with two registers; 
 if input operand information of said scalar integer instruction is utilized after execution of said scalar integer instruction, formatting said scalar integer instruction to specify execution of said scalar integer instruction with three registers. 
 
     
     
         12 . The method of  claim 7  wherein said method is performed on a processing core of a semiconductor chip having multiple processing cores. 
     
     
         13 . The method of  claim 12  wherein said processing core is a CISC processing core. 
     
     
         14 . The method of  claim 7  further comprising effecting:
 first data paths between said vector register bank and a vector execution unit in response to said determination of whether said vector instruction is to be executed with two registers or three registers; 
 second data paths between said scalar integer register bank and a scalar integer execution unit in response to said determination of whether said scalar integer instruction is to be executed with two registers or three registers. 
 
     
     
         15 . A computing system having:
 a flat panel display;   a hard disk drive; and,   a processing core having   a) logic circuitry to identify whether vector instructions and integer scalar instructions are to be executed with two registers or three registers;   b) steering circuitry coupled to said logic circuitry, said steering circuitry to control:
 i) first data paths between scalar integer execution units and a scalar integer register bank such that two registers are accessed from said scalar register bank if two register execution is identified for said scalar integer instructions or three registers are accessed from said scalar integer register bank if three register execution is identified for said scalar integer instructions; 
 ii) second data paths between vector execution units and a vector register bank such that two registers are accessed from said vector register bank if two register execution is identified for said vector instructions or three registers are accessed from said vector register bank if three register execution is identified for said vector instructions. 
   
     
     
         16 . The processing core of  claim 15  wherein said integer scalar instructions include any of:
 logical AND NOT; 
 bit field extract; 
 zero high bits starting with specified bit position; 
 parallel bits deposit; 
 parallel bits extract; 
 shift. 
 
     
     
         17 . The processing core of  claim 15  wherein said processing core is one of a plurality of processing cores implemented on said semiconductor chip. 
     
     
         18 . The processing core of  claim 15  where, in the case of three register execution, a third register is identified in prefix information of its respective instruction. 
     
     
         19 . The processing core of  claim 15  where said logic circuitry is located within a decode stage of said processing core. 
     
     
         20 . The processing core of  claim 19  wherein said processing core is a CISC processing core.