Semiconductor memory device and method of manufacturing the same

Abstract

Provided are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a semiconductor substrate including a first active region and a second active region, a gate electrode including a silicide layer formed on the first active region and a resistor pattern formed on the second active region. A distance from a top surface of the semiconductor substrate to a top surface of the resistor pattern is smaller than a distance from a top surface of the semiconductor substrate to a top surface of the gate electrode.

1 . A semiconductor memory device, comprising:
 a semiconductor substrate including a first active region and a second active region;   a gate electrode including a silicide layer formed on the first active region; and   a resistor pattern formed on the second active region,   wherein a distance from a top surface of the semiconductor substrate to a top surface of the resistor pattern is smaller than a distance from a top surface of the semiconductor substrate to a top surface of the gate electrode.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the gate electrode includes a first gate conductive pattern, an intergate insulating pattern, a second gate conductive pattern, a third gate conductive pattern and the silicide layer that are sequentially stacked and wherein the resistor pattern is formed of a same material as at least one of the first gate conductive pattern, the second gate conductive pattern and the third gate conductive pattern. 
     
     
         3 . The semiconductor memory device of  claim 2 , wherein the resistor pattern includes a lower resistor pattern formed of the same material as the first gate conductive pattern and an upper resistor pattern formed of the same material as the third gate conductive pattern and wherein a top surface of the resistor pattern is lower than a top surface of the third gate conductive pattern. 
     
     
         4 . The semiconductor memory device of  claim 2 , wherein a top surface of the semiconductor substrate of one side of the resistor pattern is lower than a top surface of the semiconductor substrate of one side of the gate electrode. 
     
     
         5 . The semiconductor memory device of  claim 2 , wherein the semiconductor substrate includes a first portion under the resistor pattern and a second portion of one side of the resistor pattern and wherein a top surface of the second portion is lower than a top surface of the first portion. 
     
     
         6 . The semiconductor memory device of  claim 5 , wherein a distance from the top surface of the first portion of the semiconductor substrate to a top surface of the resistor pattern is smaller than a distance from a top surface of the semiconductor substrate under the gate electrode to the top surface of the gate electrode. 
     
     
         7 . The semiconductor memory device of  claim 2 , wherein the semiconductor substrate includes a device isolation layer defining the first active region and the second active region and wherein a top surface of the device isolation layer adjacent to the second active region is lower than a top surface of the device isolation layer adjacent to the first active region. 
     
     
         8 . The semiconductor memory device of  claim 7 , wherein the resistor pattern is spaced apart from the device isolation layer. 
     
     
         9 . The semiconductor memory device of  claim 7 , wherein a distance between a bottom surface of the resistor pattern and the top surface of the semiconductor substrate is smaller than one tenth of a thickness of the device isolation layer. 
     
     
         10 . The semiconductor memory device of  claim 2 , further comprising:
 a gate insulating layer formed between the gate electrode and the first active region; and   a buffer insulating layer formed between the resistor pattern and the second active region,   wherein a thickness of the gate insulating layer is different from a thickness of the buffer insulating layer.