Signaling with Superimposed Clock and Data Signals

Abstract

A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal.

1 . A data transmission circuit, comprising:
 a data driver to receive a data signal having an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate, and to drive the data signal onto one or more output paths;   a clock driver to receive a clock signal having a frequency N times the associated symbol rate, where N is an integer, and to drive the clock signal onto the one or more output paths simultaneously with the data signal; and   a variable delay circuit to adjust a phase of the clock signal with respect to the data signal.   
     
     
         2 . The data transmission circuit of  claim 1 , wherein the data driver comprises a symbol-rate or fractionally spaced linear equalizer to equalize the data signal. 
     
     
         3 . The data transmission circuit of  claim 1 , wherein the variable delay circuit comprises a phase interpolator to adjust a phase of the clock signal and to provide the phase-adjusted clock signal to a data retimer coupled to the data driver. 
     
     
         4 . The data transmission circuit of  claim 1 , further comprising a combiner that superimposes the phase-adjusted clock signal onto the data signal to produce a combined signal, and outputs the combined signal to an interface connectable to the one or more output paths. 
     
     
         5 . The data transmission circuit of  claim 4 , wherein the combiner comprises a wired-OR connection of the outputs of clock driver and data driver. 
     
     
         6 . The data transmission circuit of  claim 1 , wherein the one or more output paths comprise one or more transmission lines. 
     
     
         7 . The data transmission circuit of  claim 1 , wherein N is an integer greater than one. 
     
     
         8 . The data transmission circuit of  claim 1 , wherein the variable delay circuit is also operable to receive a feedback signal from a receiver, and adjust the phase of the clock signal based at least on the feedback signal. 
     
     
         9 . The data transmission circuit of  claim 2 , wherein the data driver is also operable to receive a feedback signal from a receiver, and adjust the equalizer based at least on the feedback signal. 
     
     
         10 . A method of transmitting data, comprising:
 receiving for transmission a data signal having an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate;   receiving for transmission a clock signal having a frequency N times the associated symbol rate, where N is an integer;   adjusting a phase of the clock signal to produce a phase-adjusted clock signal; and   simultaneously driving the data signal and the phase-adjusted clock signal onto one or more output paths.   
     
     
         11 . A computer readable medium containing circuit description data that, when operated on by a circuit compiler program being executed by a processor, synthesizes a data transmission circuit that includes:
 a data driver to receive a data signal having an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate, and to drive the data signal onto one or more output paths;   a clock driver to receive a clock signal having a frequency N times the associated symbol rate, where N is an integer, and to drive the clock signal onto the one or more output paths simultaneously with the data signal; and   a variable delay circuit to adjust a phase of the clock signal with respect to the data signal.