Multiplication of Complex Numbers Represented in Floating Point

Abstract

A multiplier circuit that operates on a novel complex data format where the real and imaginary parts of the source and result operands are represented by single precision floating point numbers. The invention provides direct support for complex numbers in floating point representation, thus reducing the number of instructions and processor cycles with improved performance.

1 . A complex multiplier circuit comprising of:
 a plurality of floating point multipliers, each operable to multiply two 32 bit single precision floating point operands SRC 1  and SRC 2  generating a result, and   a plurality of floating point adders, each operable to add two floating point operands SRC 1  and SRC 2  generating a sum.   
     
     
         2 . The complex multiplier circuit of  claim 1 , wherein:
 the number of floating point multipliers is four.   
     
     
         3 . The complex multiplier circuit of  claim 1 , wherein:
 the number of floating point adders is two.   
     
     
         4 . The complex multiplier circuit of  claim 1 , wherein:
 the SRC 1  and SRC 2  inputs to the floating point multipliers are single precision floating point numbers, where each number represents the real or imaginary part of a complex number.   
     
     
         5 . The complex multiplier circuit of  claim 1 , wherein:
 SRC 1  of the first floating point multiplier is the real part of the first operand,   SRC 2  of the first floating point multiplier is the real part of the second operand,   SRC 1  of the second floating point multiplier is the imaginary part of the first operand,   SRC 2  of the second floating point multiplier is the imaginary part of the second operand,   SRC 1  of the third floating point multiplier is the real part of the second operand,   SRC 2  of the third floating point multiplier is the imaginary part of the first operand,   SRC 1  of the fourth floating point multiplier is the imaginary part of the second operand, and   SRC 2  of the fourth floating point multiplier is the real part of the first operand.   
     
     
         6 . The complex multiplier circuit of  claim 1 , wherein:
 SRC 1  of the first floating point adder is the result from the first floating point multiplier,   SRC 2  of the first floating point adder is the result from the second floating point multiplier,   SRC 1  of the second floating point adder is the result from the third floating point multiplier, and   SRC 2  of the second floating point adder is the result from the fourth floating point multiplier.   
     
     
         7 . The complex multiplier circuit of  claim 6 , wherein:
 bit  31  of the SRC 2  input to the first floating point adder is inverted.   
     
     
         8 . The complex multiplier circuit of  claim 6 , wherein:
 the sum of the first floating point adder is the real part of the result of the complex multiply, and   the sum of the second floating point adder is the imaginary part of the result of the complex multiply.