Systems, methods, and apparatuses for in-band data mask bit transmission

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array.

1 . An integrated circuit comprising:
 logic to issue a partial write command to a volatile memory device; and   logic to generate a partial write frame responsive to the partial write command, wherein the partial write frame includes m unit intervals to transfer partial write data and n unit intervals to transfer data mask bits and further wherein at least some of the data mask bits are repeated in more than one of the n unit intervals.   
     
     
         2 . The integrated circuit of  claim 1 , wherein each of the n unit intervals includes a copy of the data mask bits. 
     
     
         3 . The integrated circuit of  claim 2 , wherein each of the m unit intervals includes a byte of partial write data. 
     
     
         4 . The integrated circuit of  claim 3 , wherein each of the n unit intervals includes a data mask bit corresponding to each of the m bytes of partial write data. 
     
     
         5 . The integrated circuit of  claim 4 , wherein m is four and n is four. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the integrated circuit comprises a memory controller. 
     
     
         7 . The integrated circuit of  claim 6 , wherein the volatile memory device comprises a random access memory device. 
     
     
         8 . An integrated circuit comprising:
 a memory core;   input/output logic coupled with the memory core, the input/output logic capable of receiving a partial write frame including m unit intervals of partial write data and n unit intervals of data mask bits, wherein a first unit interval of the n unit intervals includes a first set of data mask bits and a second unit interval of the n unit intervals includes a second set of data mask bits; and   enable logic coupled with the input/output logic, the enable logic to enable a write to the memory core based, at least in part, on whether the first set of data mask bits matches the second set of data mask bits.   
     
     
         9 . The integrated circuit of  claim 8 , wherein each of the m unit intervals includes a byte of partial write data. 
     
     
         10 . The integrated circuit of  claim 9 , wherein each of the n unit intervals includes a set of data mask bits corresponding to the m bytes of partial write data. 
     
     
         11 . The integrated circuit of  claim 10 , wherein the enable logic is capable of enabling a write to the memory core based, at least in part, on whether the n sets of data mask bits match. 
     
     
         12 . The integrated circuit of  claim 11 , wherein m is four and n is four. 
     
     
         13 . The integrated circuit of  claim 8 , wherein the integrated circuit comprises a dynamic random access memory device. 
     
     
         14 . A method comprising:
 issuing a partial write command to a volatile memory device;   generating a partial write frame responsive to the partial write command, wherein the partial write frame includes m unit intervals to transfer partial write data and n unit intervals to transfer data mask bits and further wherein at least some of the data mask bits are repeated in more than one of the n unit intervals; and   transferring the partial write frame to the volatile memory device.   
     
     
         15 . The method of  claim 14 , wherein each of the n unit intervals includes a copy of the data mask bits. 
     
     
         16 . The method of  claim 15 , wherein each of the m unit intervals includes a byte of partial write data. 
     
     
         17 . The method of  claim 16 , wherein each of the n unit intervals includes a data mask bit corresponding to each of the m bytes of partial write data. 
     
     
         18 . The method of  claim 17 , wherein m is four and n is four. 
     
     
         19 . The method of  claim 14 , wherein the volatile memory device comprises a random access memory device. 
     
     
         20 . A system comprising:
 a host including
 logic to issue a partial write command to a dynamic random access memory device, and 
 logic to generate a partial write frame responsive to the partial write command, wherein the partial write frame includes m unit intervals to transfer partial write data and n unit intervals to transfer data mask bits and further wherein at least some of the data mask bits are repeated in more than one of the n unit intervals; and the dynamic random access memory device to receive the partial write data frame. 
   
     
     
         21 . The system of  claim 20 , wherein each of the n unit intervals includes a set of the data mask bits and each of the m unit intervals includes a byte of partial write data. 
     
     
         22 . The system of  claim 21 , wherein each of the n unit intervals includes a data mask bit corresponding to each of the m bytes of partial write data. 
     
     
         23 . The system of  claim 22 , wherein m is four and n is four. 
     
     
         24 . The system of claim, wherein the dynamic random access memory device includes
 a memory core;   input/output logic coupled with the memory core, the input/output logic capable of receiving the partial write frame; and   enable logic coupled with the input/output logic, the enable logic to enable a write to the memory core based, at least in part, on whether the n data mask bit sets match.