Input/output core design and method of manufacture therefor

Abstract

One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.

1 . An input/output cell, comprising:
 an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides;   input/output transistors positioned within the input/output layout boundary over the substrate;   first and second power conductors located over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides; and   first and second ground conductors located over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides.   
     
     
         2 . The input/output cell recited in  claim 1 , further including a bond pad positioned within the input/output layout boundary over the substrate. 
     
     
         3 . The input/output cell recited in  claim 2 , wherein the bond pad is square. 
     
     
         4 . The input/output cell recited in  claim 2 , wherein two edges of the bond pad face the input/output transistors. 
     
     
         5 . The input/output cell recited in  claim 2 , wherein the bond pad is positioned proximate a corner of the input/output layout boundary. 
     
     
         6 . The input/output cell recited in  claim 1 , wherein the input/output layout boundary forms a rectangle. 
     
     
         7 . The input/output cell recited in  claim 1 , wherein the input/output layout boundary forms a square. 
     
     
         8 . The input/output cell recited in  claim 1 , further including a first signal pin located proximate the first side and a second signal pin located proximate the third side. 
     
     
         9 . The input/output cell recited in  claim 1 , wherein each of the input/output transistors is oriented in a same direction. 
     
     
         10 . A method for manufacturing an input/output cell, comprising:
 delineating an input/output layout boundary on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides;   positioning input/output transistors within the input/output layout boundary over the substrate;   forming first and second power conductors over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides; and   forming first and second ground conductors over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides.   
     
     
         11 . The method recited in  claim 10  further including creating a bond pad within the input/output layout boundary over the substrate, at least two edges of the bond pad facing the input/output transistors. 
     
     
         12 . The method recited in  claim 11 , wherein the bond pad is square. 
     
     
         13 . The method recited in  claim 11 , wherein the bond pad is positioned proximate a corner of the input/output layout boundary. 
     
     
         14 . The method recited in  claim 10 , wherein the input/output layout boundary forms a square. 
     
     
         15 . The method recited in  claim 10 , further including creating a first signal pin proximate the first side and a second signal pin proximate the third side.