Implementing phase locked loop (pll) with enhanced locking capability with a wide range dynamic reference clock

Abstract

A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.

1 . A method for implementing a phase locked loop (PLL) with enhanced locking capability with a wide range dynamic reference clock comprising:
 applying a differential filter VCO control voltage to a Voltage Controlled Oscillator (VCO);   providing a plurality of filter comparators comparing the differential filter VCO control voltage values,   providing a respective gate enable signal responsive to the compared differential filter voltage values;   applying a clock signal to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock; and   providing counter values to the VCO to select a respective frequency range for the VCO.   
     
     
         2 . The method as recited in  claim 1  wherein applying a clock signal to an up/down counter responsive to the respective gate enable signal and the wide range reference clock includes applying a decrement clock signal responsive to the frequency of the reference clock ramping down from a normal mode reference clock frequency to a low power mode reference clock frequency. 
     
     
         3 . The method as recited in  claim 1  wherein applying a clock signal to an up/down counter responsive to the respective gate enable signal and the wide range reference clock includes applying an increment clock signal responsive to the frequency of the reference clock ramping up from a low power mode reference clock frequency to a normal mode reference clock frequency. 
     
     
         4 . The method as recited in  claim 1  wherein applying a clock signal to an up/down counter responsive to the respective gate enable signal and the wide range reference clock includes applying the wide range dynamic reference clock to a frequency divider to provide a divided down reference clock, said divided down reference clock to selectively increment or decrement the up/down counter. 
     
     
         5 . The method as recited in  claim 4  includes providing said frequency divider with a selected value based upon the reference clock ramp between the normal mode reference clock frequency and the low power mode reference clock frequency. 
     
     
         6 . The method as recited in  claim 4  includes providing said frequency divider with a selected value of 10 where the reference clock ramps from the normal mode reference clock frequency of 250 MHz and the low power mode reference clock frequency 50 MHz in 1 micro-second (μs), and said VCO includes eight (8) frequency bands. 
     
     
         7 . A phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock comprising:
 a Voltage Controlled Oscillator (VCO) receiving a differential filter VCO control voltage;   a plurality of filter comparators comparing the differential filter VCO control voltage values,   said plurality of filter comparators generating a respective gate enable signal responsive to the compared differential filter VCO control voltage values; and   an up/down counter receiving a clock signal responsive to said respective gate enable signal and the wide range dynamic reference clock; and said up/down counter providing counter values to said VCO for selecting a respective frequency range for the VCO.   
     
     
         8 . The phase locked loop (PLL) circuit as recited in  claim 7  includes a frequency divider for dividing a received wide range dynamic reference clock frequency signal and generating a divided reference clock frequency signal. 
     
     
         9 . The phase locked loop (PLL) circuit as recited in  claim 8  wherein said frequency divider has a selected value based upon the reference clock ramp between the normal mode reference clock frequency and the low power mode reference clock frequency. 
     
     
         10 . The phase locked loop (PLL) circuit as recited in  claim 9  wherein said frequency divider has a selected value of 10 where the reference clock ramps from the normal mode reference clock frequency of 250 MHz and the low power mode reference clock frequency 50 MHz in 1 micro-second (μs), and said VCO includes eight (8) frequency bands. 
     
     
         11 . The phase locked loop (PLL) circuit as recited in  claim 7  includes a first latch coupled to a first pair of said filter comparators and a second latch coupled to a second pair of said filter comparators. 
     
     
         12 . The phase locked loop (PLL) circuit as recited in  claim 11  includes a first AND gate coupled to said first latch receiving said respective gate enable signal, and a second AND gate coupled to said second latch receiving said respective gate enable signal. 
     
     
         13 - 14 . (canceled) 
     
     
         15 . A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
 a phase locked loop (PLL) circuit tangibly embodied in the machine readable medium used in the design process, said PLL circuit for implementing enhanced locking capability with a wide range dynamic reference clock, said PLL circuit comprising:   a Voltage Controlled Oscillator (VCO) receiving a differential filter VCO control voltage;   a plurality of filter comparators comparing the differential filter VCO control voltage values,   said plurality of filter comparators generating a respective gate enable signal responsive to the compared differential filter VCO control voltage values; and   an up/down counter receiving a clock signal responsive to said respective gate enable signal and the wide range dynamic reference clock; and said up/down counter providing counter values to said VCO for selecting a respective frequency range for the VCO, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said PLL circuit.   
     
     
         16 . The design structure of  claim 15 , wherein the design structure comprises a netlist, which describes said PLL circuit. 
     
     
         17 . The design structure of  claim 15 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. 
     
     
         18 . The design structure of  claim 15 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. 
     
     
         19 . The design structure of  claim 15 , includes a frequency divider for dividing a received wide range dynamic reference clock frequency signal and generating a divided reference clock frequency signal, said frequency divider has a selected value based upon the reference clock ramp between the normal mode reference clock frequency and the low power mode reference clock frequency. 
     
     
         20 . The design structure of  claim 15 , includes logic gates coupled to said frequency divider and said plurality of filter comparators for generating said clock signal applied to said up/down counter.