Method and apparatus for reducing the processing rate of a chip-level equalization receiver

Abstract

A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.

1 . A code division multiple access (CDMA) receiver comprising:
 an antenna component configured to receive a data signal associated with a chip rate;   circuitry configured to define a plurality of streams of data samples corresponding to the received data signal at the chip rate;   a combiner component configured to combine the plurality of streams of data samples into a data stream of combined samples at the chip rate; and   a one times chip rate normalized least mean square (NLMS) equalizer configured to equalize the data stream of combined samples.   
     
     
         2 . The receiver of  claim 1  wherein:
 the circuitry configured to define a plurality of streams of data samples includes:
 a sampling device configured to sample the received data signal at a multiple M of the chip rate, where M is an integer greater than 1, to produce an over-sampled stream of data samples; and 
 a serial-to-parallel (S/P) converter configured to split the over-sampled stream of data samples into M streams of data samples; and 
 
 the combiner component is configured to combine the M streams of data samples in connection with producing the data stream of combined samples at the chip rate. 
 
     
     
         3 . The receiver of  claim 2  wherein:
 the antenna component is configured as a single antenna; 
 the sampling device is configured to sample the received data signal that is received by the antenna at twice the chip rate; and 
 the serial-to-parallel (S/P) converter is configured to split the over-sampled stream of data samples into even and odd streams of data samples. 
 
     
     
         4 . The receiver of  claim 2  wherein the combiner component includes:
 M multipath combiners, each configured to combine multipath or delayed replicates of signal samples with respect to a respective stream of data samples of the M streams of data samples to produce a combined multipath version of the respective stream of data samples; and 
 an over-sample combiner configured to combine the combined multipath versions of the M streams of data samples in connection with producing the data stream of combined samples at the chip rate. 
 
     
     
         5 . The receiver of  claim 4  wherein:
 the antenna component is configured as a single antenna; 
 the sampling device is configured to sample the received data signal that is received by the antenna at twice the chip rate; and 
 the serial-to-parallel (S/P) converter is configured to split the over-sampled stream of data samples into even and odd streams of data samples. 
 
     
     
         6 . The receiver of  claim 1  wherein:
 the antenna component is configured with N antennas; 
 the circuitry configured to define a plurality of streams of data samples includes:
 N sampling devices, each configured to sample the received data signal as received from a respective one of the N antennas at a multiple M of the chip rate, where M is an integer greater that 1, such that the N sampling devices produce N respective over-sampled streams of data samples; and 
 N serial-to-parallel (S/P) converters, each configured to split a respective over-sampled stream of data samples into M streams of data samples; and 
 
 the combiner component includes:
 N combiners, each configured to combine the M streams of data samples derived from a respective over-sampled stream of data samples such that the N combiners produce N combined data streams, and 
 a diversity data stream combiner configured to combine the N combined data streams in connection with producing the data stream of combined samples at the chip rate. 
 
 
     
     
         7 . The receiver of  claim 6  wherein:
 each sampling device is configured to sample the received data signal that is received by a respective antenna at twice the chip rate; and 
 each serial-to-parallel (S/P) converter is configured to split the respective over-sampled stream of data samples into even and odd streams of data samples. 
 
     
     
         8 . The receiver of  claim 7  wherein the antenna component is configured with two (2) antennas. 
     
     
         9 . The receiver of  claim 6  wherein:
 each of the N combiners includes:
 M multipath combiners, each configured to combine multipath or delayed replicates of signal samples with respect to a respective stream of data samples of the respective M streams of data samples to produce a combined multipath version of the respective stream of data samples; and 
 an over sample combiner configured to combine the combined multipath versions of the M streams of data samples such that each of the N combiners produces a respective over-sampled combined multipath versions of a respective over-sampled streams of data; and 
 
 the diversity data stream combiner is configured to combine the N over-sampled combined multipath versions of the N over-sampled streams of data in connection with producing the data stream of combined samples at the chip rate. 
 
     
     
         10 . The receiver of  claim 9  wherein:
 each sampling device is configured to sample the received data signal that is received by a respective antenna at twice the chip rate; and 
 each serial-to-parallel (S/P) converter is configured to split the respective over-sampled stream of data samples into even and odd streams of data samples. 
 
     
     
         11 . The receiver of  claim 10  wherein the antenna component is configured with two (2) antennas. 
     
     
         12 . A wireless communication apparatus comprising the receiver of  claim 1 . 
     
     
         13 . A method of equalizing received data signals in a code division multiple access (CDMA) wireless communications comprising:
 receiving a data signal associated with a chip rate;   defining a plurality of streams of data samples corresponding to the received data signal at the chip rate;   combining the plurality of streams of data samples into a data stream of combined samples at the chip rate; and   using a one times chip rate normalized least mean square (NLMS) equalizer to equalize the data stream of combined samples.   
     
     
         14 . The method of  claim 13  wherein:
 the defining a plurality of streams of data samples includes:
 sampling the received data signal at a multiple M of the chip rate, where M is an integer greater than 1, to produce an over-sampled stream of data samples; and 
 splitting the over-sampled stream of data samples into M streams of data samples; and 
 
 the combining includes combining the M streams of data samples in connection with producing the data stream of combined samples at the chip rate. 
 
     
     
         15 . The method of  claim 14  wherein the combining includes:
 for each of the M streams of data samples, combining multipath or delayed replicates of signal samples to produce a combined multipath version of the respective stream of data samples; and 
 combining the combined multipath versions of the M streams of data samples in connection with producing the data stream of combined samples at the chip rate. 
 
     
     
         16 . The method of  claim 15  wherein:
 the sampling the received data signal is at twice the chip rate; and 
 the over-sampled stream of data samples is split into even and odd streams of data samples. 
 
     
     
         17 . The method of  claim 13  wherein:
 the defining a plurality of streams of data samples includes:
 with respect to each of N versions of the data signal received by a different one of N antennas, sampling the received data signal at a multiple M of the chip rate, where M is an integer greater than 1, such that N respective over-sampled streams of data samples are produced; and 
 splitting each respective over-sampled stream of data samples into a set of M streams of data samples; and 
 
 the combining includes:
 with respect to each set of M streams of data samples, combining the M of streams of data samples derived from a respective over-sampled stream of data samples such that N combined data streams are produced, and 
 diversity combining the N combined data streams in connection with producing the data stream of combined samples at the chip rate. 
 
 
     
     
         18 . The method of  claim 17  wherein:
 the combining with respect to each set of M streams of data samples includes:
 for each of the M streams of data, combining multipath or delayed replicates of signal samples to produce a combined multipath version of the respective stream of data samples; and 
 over sample combining the combined multipath versions of the M of streams of data samples such that a respective over-sampled combined multipath versions of a respective over-sampled streams of data is produced; and 
 
 the diversity combining includes combining the over-sampled combined multipath versions of the N over-sampled streams of data in connection with producing the data stream of combined samples at the chip rate. 
 
     
     
         19 . The method of  claim 18  wherein:
 each version of the received data signal is sampled at twice the chip rate; and 
 each respective over-sampled stream of data samples is split into even and odd streams of data samples. 
 
     
     
         20 . The method of  claim 19  performed with respect to a version of the received signal with respect to two (2) antennas.